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Editing 22 nm lithography process
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== References == | == References == | ||
− | * IEDM 2012 | + | * Narasimha, S., et al. "22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL." Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012. |
− | * IEDM 2014 | + | * Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014. |
− | * ISSCC | + | * Hamzaoglu, Fatih, et al. "13.1 a 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International. IEEE, 2014. |
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[[category:lithography]] | [[category:lithography]] |