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Editing 20 nm lithography process
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== Industry == | == Industry == | ||
− | {{ | + | {{scrolling table/top|style=text-align: right; | first=Fab |
− | + | |Wafer | |
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− | + | |Contacted Gate Pitch | |
− | + | |Interconnect Pitch (M1P) | |
− | + | |SRAM bit cell | |
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}} | }} | ||
+ | {{scrolling table/mid}} | ||
+ | |- | ||
+ | ! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="4" | 300mm | ||
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+ | ! Value !! [[28 nm]] Δ !! Value !! [[28 nm]] Δ | ||
+ | |- | ||
+ | | 64 nm || 0.71x || 87 nm || 0.71x | ||
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+ | | 64 nm || 0.67x || 67 nm || 0.70x | ||
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+ | | ? µm² || ?x || 0.081 µm²<ref name="tsmc">Chang, Jonathan, et al. "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-V MIN applications." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. IEEE, 2013.</ref> || 0.64x | ||
+ | {{scrolling table/end}} | ||
=== TSMC === | === TSMC === | ||
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{| class="collapsible collapsed wikitable" | {| class="collapsible collapsed wikitable" | ||
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− | ! colspan="2" | TSMC 112 Mib SRAM demo 20 nm wafer | + | ! colspan="2" | TSMC 112 Mib SRAM demo 20 nm wafer<ref name="tsmc" /> |
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* MediaTek | * MediaTek | ||
** {{mediatek|Helio}} | ** {{mediatek|Helio}} | ||
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{{expand list}} | {{expand list}} | ||
== 20 nm Microarchitectures== | == 20 nm Microarchitectures== | ||
{{expand list}} | {{expand list}} | ||
− | + | [[Category:Lithography]] | |
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− | [[ |