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Editing 16 nm lithography process
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== Industry == | == Industry == | ||
− | + | {{scrolling table/top|style=text-align: right; | first=Fab | |
− | {{ | + | |Wafer |
− | + | | | |
− | + | |Fin Pitch | |
− | + | |Fin Width | |
− | + | |Fin Height | |
− | + | |Contacted Gate Pitch | |
− | + | |Interconnect Pitch (M1P) | |
− | + | |SRAM bit cell | |
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}} | }} | ||
+ | {{scrolling table/mid}} | ||
+ | |- | ||
+ | ! colspan="2" | [[TSMC]] | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="2" | 300mm | ||
+ | |- | ||
+ | ! Value !! [[20 nm]] Δ | ||
+ | |- | ||
+ | | 48 nm || rowspan="3" | N/A | ||
+ | |- | ||
+ | | ? nm | ||
+ | |- | ||
+ | | 37 nm | ||
+ | |- | ||
+ | | 90 nm || 1.03x | ||
+ | |- | ||
+ | | 64 nm || 0.96x | ||
+ | |- | ||
+ | | 0.07 µm² || 0.86x | ||
+ | {{scrolling table/end}} | ||
=== TSMC === | === TSMC === | ||
− | + | TSMC demonstrated their 128 Mebibit [[SRAM]] wafer from their 16 nm HKMG FinFET process at the 2014 IEEE ISSCC. | |
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{| class="collapsible collapsed wikitable" | {| class="collapsible collapsed wikitable" | ||
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== 16 nm Microprocessors== | == 16 nm Microprocessors== | ||
− | * | + | * PEZY |
− | ** {{ | + | ** {{pezy|PEZY-SC2}} |
* MediaTek | * MediaTek | ||
** {{mediatek|Helio}} | ** {{mediatek|Helio}} | ||
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{{expand list}} | {{expand list}} | ||
== 16 nm Microarchitectures== | == 16 nm Microarchitectures== | ||
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{{expand list}} | {{expand list}} | ||
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− | [[ | + | [[Category:Lithography]] |