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== Industry == | == Industry == | ||
− | + | {{scrolling table/top|style=text-align: right; | first=Fab | |
− | {{ | + | |Wafer |
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− | + | |Fin Pitch | |
− | + | |Fin Width | |
− | + | |Fin Height | |
− | + | |Contacted Gate Pitch | |
− | + | |Interconnect Pitch (M1P) | |
− | + | |SRAM bit cell | |
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}} | }} | ||
+ | {{scrolling table/mid}} | ||
+ | |- | ||
+ | ! colspan="2" | [[TSMC]] | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="2" | 300mm | ||
+ | |- | ||
+ | ! Value<ref>TechInsights/Chipworks, Kevin Gibb, The ConFab 2016</ref> !! [[20 nm]] Δ | ||
+ | |- | ||
+ | | 48 nm || rowspan="3" | N/A | ||
+ | |- | ||
+ | | ? nm | ||
+ | |- | ||
+ | | 37 nm | ||
+ | |- | ||
+ | | 90 nm || 1.03x | ||
+ | |- | ||
+ | | 70 nm || 1.09x | ||
+ | |- | ||
+ | | 0.07 µm²<ref name="tsmc">Chen, Yen-Huei, et al. "A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 170-177.</ref> || 0.55x | ||
+ | {{scrolling table/end}} | ||
=== TSMC === | === TSMC === | ||
− | + | TSMC demonstrated their 256 Mebibit [[SRAM]] wafer from their 7nm HKMG FinFET process. Their chip makes use of 34% of the area of their [[16 nm process]] demo chip counterpart. | |
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{| class="collapsible collapsed wikitable" | {| class="collapsible collapsed wikitable" | ||
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− | ! colspan="2" | TSMC | + | ! colspan="2" | TSMC 256Mb SRAM demo wafer<ref name="tsmc" /> |
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<table class="wikitable"> | <table class="wikitable"> | ||
<tr><th>Technology</th><td>16 nm HK-MG FinFET</td></tr> | <tr><th>Technology</th><td>16 nm HK-MG FinFET</td></tr> | ||
− | <tr><th>Metal scheme</th><td> | + | <tr><th>Metal scheme</th><td>1P7M</td></tr> |
<tr><th>Supply voltage</th><td>0.85 V (core)<br>1.8 V (i/o)</td></tr> | <tr><th>Supply voltage</th><td>0.85 V (core)<br>1.8 V (i/o)</td></tr> | ||
<tr><th>Bit cell size</th><td>0.07 µm²</td></tr> | <tr><th>Bit cell size</th><td>0.07 µm²</td></tr> | ||
<tr><th>macro configs</th><td>4096x32 MUX16<br>258 bits/BL<br>272 bits/WL</td></tr> | <tr><th>macro configs</th><td>4096x32 MUX16<br>258 bits/BL<br>272 bits/WL</td></tr> | ||
− | <tr><th>Capacity</th><td> | + | <tr><th>Capacity</th><td>256 Mib</td></tr> |
<tr><th>Test Features</th><td>Row/Column Redundancy<br>Programmable E-fuse</td></tr> | <tr><th>Test Features</th><td>Row/Column Redundancy<br>Programmable E-fuse</td></tr> | ||
<tr><th>Die Size</th><td>42.6 mm²</td></tr> | <tr><th>Die Size</th><td>42.6 mm²</td></tr> | ||
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== 16 nm Microprocessors== | == 16 nm Microprocessors== | ||
− | * | + | * PEZY |
− | ** {{ | + | ** {{pezy|PEZY-SC2}} |
* MediaTek | * MediaTek | ||
** {{mediatek|Helio}} | ** {{mediatek|Helio}} | ||
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{{expand list}} | {{expand list}} | ||
== 16 nm Microarchitectures== | == 16 nm Microarchitectures== | ||
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{{expand list}} | {{expand list}} | ||
== References == | == References == | ||
− | + | {{reflist}} | |
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− | [[ | + | [[Category:Lithography]] |