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| {{lithography processes}} | | {{lithography processes}} |
− | The '''130 nanometer (130 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[150 nm lithography process|150 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 130 nm process began in 2001. This technology was replaced by with [[110 nm lithography process|110 nm process]] (HN) in 2003 and [[90 nm lithography process|90 nm process]] (FN) in 2004. | + | The '''130 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[150 nm lithography process|150 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 130 nm process began in 2001. This technology was replaced by with [[110 nm lithography process|110 nm process]] (HN) in 2003 and [[90 nm lithography process|90 nm process]] (FN) in 2004. |
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| == Industry == | | == Industry == |
− | {{scrolling table/top|style=text-align: right; | first=Fab
| + | |
− | |Process Name
| + | === Intel === |
− | |1st Production
| + | * 200mm (8-inch) wafers |
− | |Type
| + | {| class="wikitable" |
− | |Wafer
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− | |Metal Layers
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− | |
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− | |Contacted Gate Pitch
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− | |Interconnect Pitch (M1P)
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− | |SRAM bit cell (HP)
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− | |SRAM bit cell (HD)
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− | }}
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− | {{scrolling table/mid}}
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| |- | | |- |
− | ! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Fujitsu]] !! colspan="2" | [[IBM]] / [[Infineon]] / [[UMC]] !! colspan="2" | [[Motorola]] !! colspan="2" | [[AMD]] !! colspan="2" | [[NEC]] !! colspan="2" | [[NEC]] !! colspan="2" | [[TI]] !! colspan="2" | [[TI]]
| + | | || Measurement || Scaling from [[180 nm]] |
− | |- style="text-align: center;"
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− | | colspan="2" | P860 || colspan="2" | || colspan="2" | || colspan="2" | CS-91 || colspan="2" | CMOS 9S || colspan="2" | HiPerMOS 7 || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" |
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− | |- style="text-align: center;"
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− | | colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2002 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2002 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" |
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− | |- style="text-align: center;"
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− | | colspan="8" | Bulk || colspan="2" | PDSOI || colspan="12" | Bulk
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− | |- style="text-align: center;"
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− | | colspan="22" | 200 mm
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− | |- style="text-align: center;"
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− | | colspan="2" | 6 || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | 8 || colspan="2" | 8 || colspan="2" | || colspan="2" | 5 || colspan="2" | 7 || colspan="2" | 6 || colspan="2" | 7
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| |- | | |- |
− | ! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ
| + | | Contacted Gate Pitch || 319 nm || 0.66x |
| |- | | |- |
− | | 319 nm || 0.66x || 310 nm || 0.72x || 350 nm || ?x || ? nm || ?x || 320 nm || 0.76x || 350 nm || ?x || 350 nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x | + | | Interconnect Pitch (M1P) || 345 nm || 0.69x |
| |- | | |- |
− | | 345 nm || 0.69x || 340 nm || 0.74x || 350 nm || ?x || ? nm || ?x || 320 nm || 0.73x || 350 nm || ?x || 350 nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x | + | | [[SRAM]] bit cell || 2.0 µm<sup>2</sup> || 0.36x |
− | |-
| + | |} |
− | | 2.45 µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x
| + | |
− | |-
| + | {| class="wikitable" |
− | | 2.09 µm² || 0.36x || 2.14 µm² || 0.46x || ? µm² || ?x || 1.98 µm² || 0.47x || 1.8 µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x
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− | {{scrolling table/end}}
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− | === Design Rules ===
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− | {| class="wikitable collapsible collapsed" | |
| |- | | |- |
− | ! colspan="4" | Intel 130nm Design Rules | + | ! colspan="4" | Design Rules |
| |- | | |- |
| ! Layer !! Pitch !! Thick !! Aspect Ratio | | ! Layer !! Pitch !! Thick !! Aspect Ratio |
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| == 130 nm Microprocessors== | | == 130 nm Microprocessors== |
− | * Ambric
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− | ** {{ambric|Am2000}}
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− | * AMD
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− | ** {{amd|Athlon 64}}
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− | ** {{amd|Athlon MP}}
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− | ** {{amd|Athlon XP}}
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− | ** {{amd|Athlon XP-M}}
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− | ** {{amd|Geode NX}}
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− | ** {{amd|FX}}
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− | ** {{amd|Opteron}}
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− | * Cavium
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− | ** {{cavium|OCTEON}}
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− | * HAL (Fujitsu)
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− | ** {{hal|SPARC64 V}}
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− | * IBM
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− | ** {{ibm|Power4+}}
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− | ** {{ibm|Power5}}
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− | * Intel
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− | ** {{intel|Pentium III}}
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− | ** {{intel|Pentium III-M}}
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− | ** {{intel|Pentium M}}
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− | ** {{intel|Pentium 4 Extreme Edition}}
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− | * Intrinsity
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− | ** {{intrinsity|FastMATH}}
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− | * Loongson
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− | ** {{loongson|Godson 2}}
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− | * Qualcomm
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− | ** {{qualcomm|MSM6xxx}}
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− | * SGI
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− | ** {{sgi|R14000}}
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− | ** {{sgi|R14000A}}
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− | * Sun
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− | ** {{sun|UltraSPARC IIi}}
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− | ** {{sun|UltraSPARC III Cu}}
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− | ** {{sun|UltraSPARC IIIi}}
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− |
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− | * NUDT
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− | ** {{nudt|FT-64}}
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| {{expand list}} | | {{expand list}} |
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− | == 130 nm programmable logic devices == | + | == 130 nm System on Chips== |
− | * MathStar
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− | ** {{mathstar|Builder}}
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| {{expand list}} | | {{expand list}} |
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| == 130 nm Microarchitectures == | | == 130 nm Microarchitectures == |
− | * AMD
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− | ** {{amd|K8|l=arch}}
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− | * ARM
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− | ** {{armh|ARM7|l=arch}}
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− | * IBM
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− | ** {{ibm|z990|l=arch}}
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− | * VIA Technologies
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− | ** {{via|Nehemiah|l=arch}}
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| {{expand list}} | | {{expand list}} |
− |
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− | == References ==
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− | * Tyagi, Sunit, et al. "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects." Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International. IEEE, 2000.
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− | [[category:lithography]]
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