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== Overview == | == Overview == | ||
− | First introduced between 2017-2019, the 10 nm [[process technology]] is characterized by its use of [[FinFET]] transistors with a 30-40s nm [[fin pitches]]. Those nodes typically have a [[gate pitch]] in range of 50-60s nm and a [[minimum metal pitch]] in the range of 30-40s nm | + | First introduced between 2017-2019, the 10 nm [[process technology]] is characterized by its use of [[FinFET]] transistors with a 30-40s nm [[fin pitches]]. Those nodes typically have a [[gate pitch]] in range of 50-60s nm and a [[minimum metal pitch]] in the range of 30-40s nm. |
== Industry == | == Industry == | ||
At the advanced 10nm process, there are only 3 semiconductor foundries with such manufacturing capabilities: [[Intel]], [[Samsung]], and [[TSMC]]. | At the advanced 10nm process, there are only 3 semiconductor foundries with such manufacturing capabilities: [[Intel]], [[Samsung]], and [[TSMC]]. | ||
− | Due to marketing names, geometries vary greatly between leading | + | Due to marketing names, geometries vary greatly between leading manufactures. Although both TSMC and Samsung's 10nm processes are slightly denser than Intel's 14nm in raw logic density, they are far closer to Intel's 14nm than they are to Intel's 10nm (e.g., Samsung's metal pitch just 1 nanometer shorter than Intel's 14nm). |
{{10 nm comp | {{10 nm comp | ||
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| process 2 fin pitch = 36 nm | | process 2 fin pitch = 36 nm | ||
| process 2 fin pitch Δ = 0.75x | | process 2 fin pitch Δ = 0.75x | ||
− | | process 2 fin width = | + | | process 2 fin width = |
| process 2 fin width Δ = | | process 2 fin width Δ = | ||
− | | process 2 fin height = | + | | process 2 fin height = |
− | | process 2 fin height Δ = | + | | process 2 fin height Δ = |
| process 2 gate len = | | process 2 gate len = | ||
| process 2 gate len Δ = | | process 2 gate len Δ = | ||
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Intel will leverage their initial 10nm process for their {{intel|Cannon Lake|l=arch}}-based microprocessors which are used exclusively for mobile. They will then utilize their second generation, "10nm+" process, for {{intel|Ice Lake|l=arch}}-based processors which will be used for the mainstream and server platform. | Intel will leverage their initial 10nm process for their {{intel|Cannon Lake|l=arch}}-based microprocessors which are used exclusively for mobile. They will then utilize their second generation, "10nm+" process, for {{intel|Ice Lake|l=arch}}-based processors which will be used for the mainstream and server platform. | ||
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* [https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-intels-10nm-switching-to-cobalt-interconnects/ In-depth analysis for Intel's 10nm process.] | * [https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-intels-10nm-switching-to-cobalt-interconnects/ In-depth analysis for Intel's 10nm process.] | ||
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=== Samsung === | === Samsung === | ||
[[File:ss 14-10nm.png|right|500px]] | [[File:ss 14-10nm.png|right|500px]] | ||
− | Samsung demonstrated their 128 | + | Samsung demonstrated their 128 Mebibit [[SRAM]] wafer from their 10nm FinFET process. Samsung, which unlike Intel uses LELELE (litho-etch-litho-etch-litho-etch), ramped up mass production in May of 2017. ChipWorks/TechInsight measured the CPP/MMP which came a little short of the Common Platform Alliance Paper which was presented in 2016, at 68 nm contacted gate pitch, 51 nm metal pitch, dual-depth [[shallow trench isolation]] (STI), and had single dummy gate. |
{| class="collapsible collapsed wikitable" | {| class="collapsible collapsed wikitable" | ||
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=== TSMC === | === TSMC === | ||
− | TSMC reported a poly pitch of 64 nm with a metal pitch 42 nm. TechInsight measured them at 66 nm and 44 nm respectively. 10FF is the second process to use FinFET, and is the Industry's first use of Quad-Patterning. This allows for a full node shrink, enabling a 2X increase in logic density compared to their 16nm process. | + | TSMC reported a poly pitch of 64 nm with a metal pitch 42 nm. TechInsight measured them at 66 nm and 44 nm respectively. 10FF is the second process to use FinFET, and is the Industry's first use of Quad-Patterning. This allows for a full node shrink, enabling a 2X increase in logic density compared to their 16nm process. TSMC claims the 10FF process will have 15% higher performance while consuming 35% less power. |
{{clear}} | {{clear}} | ||
[[File:10nm tsmc.jpeg|200px]] | [[File:10nm tsmc.jpeg|200px]] | ||
== 10 nm Microprocessors== | == 10 nm Microprocessors== | ||
− | + | * Apple | |
− | {{ | + | ** {{apple|ax|A10X}} |
− | + | ** {{apple|A11 Bionic}} | |
− | + | * HiSilicon | |
− | + | ** {{hisil|Kirin}} | |
− | + | * MediaTek | |
− | + | ** {{mediatek|Helio}} | |
− | + | * Qualcomm | |
− | + | ** {{qualcomm|Snapdragon 800}} | |
− | + | ** {{qualcomm|Centriq}} | |
− | + | * Xiaomi | |
− | + | ** {{xiaomi|Surge}} | |
− | }} | + | * Samsung |
+ | ** {{samsung|Exynos 9}} | ||
{{expand list}} | {{expand list}} | ||
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*** {{intel|Ice Lake (client)|l=arch}} | *** {{intel|Ice Lake (client)|l=arch}} | ||
*** {{intel|Tiger Lake|l=arch}} | *** {{intel|Tiger Lake|l=arch}} | ||
− | + | ** {{intel|Alder Lake|l=arch}} | |
*** {{intel|Ice Lake (server)|l=arch}} | *** {{intel|Ice Lake (server)|l=arch}} | ||
*** {{intel|Sapphire Rapids|l=arch}} | *** {{intel|Sapphire Rapids|l=arch}} | ||
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*** <s>{{intel|Knights Hill|l=arch}}</s> | *** <s>{{intel|Knights Hill|l=arch}}</s> | ||
** GPU | ** GPU | ||
− | *** {{intel| | + | *** {{intel|Artic Sound|l=arch}} |
*** {{intel|Jupiter Sound|l=arch}} | *** {{intel|Jupiter Sound|l=arch}} | ||
* Qualcomm | * Qualcomm | ||
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* Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016). | * Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016). | ||
* Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017. | * Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017. | ||
− | * Samsung's actual | + | * Samsung's actual transitor size was measured by ChipWorks/TechInsight based on the [[Qualcomm]] {{qualcomm|Snapdragon 835}} which is manufactured on Samsung's 10nm process. |
* [http://www.techinsights.com/technology-intelligence/overview/latest-reports/tsmc-10-nm-process/ TechInsights TSMC 10 nm Process Analysis] | * [http://www.techinsights.com/technology-intelligence/overview/latest-reports/tsmc-10-nm-process/ TechInsights TSMC 10 nm Process Analysis] | ||
[[category:lithography]] | [[category:lithography]] |