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{{lithography processes}} | {{lithography processes}} | ||
− | The '''10 nanometer (10 nm) lithography process''' is a | + | The '''10 nanometer (10 nm) lithography process''' is a semiconductor manufacturing [[process node]] serving as [[process shrink|shrink]] from the [[14 nm process]]. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 10 nm node is currently being introduced and is set to get replaced by the [[7 nm process]] in 2019. |
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== Industry == | == Industry == | ||
At the advanced 10nm process, there are only 3 semiconductor foundries with such manufacturing capabilities: [[Intel]], [[Samsung]], and [[TSMC]]. | At the advanced 10nm process, there are only 3 semiconductor foundries with such manufacturing capabilities: [[Intel]], [[Samsung]], and [[TSMC]]. | ||
− | Due to marketing names, geometries vary greatly between leading | + | Due to marketing names, geometries vary greatly between leading manufactures. Although both TSMC and Samsung's 10nm processes are slightly denser than Intel's 14nm in raw logic density, they are far closer to Intel's 14nm than they are to Intel's 10nm (e.g., Samsung's metal pitch just 1 nanometer shorter than Intel's 14nm). |
{{10 nm comp | {{10 nm comp | ||
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| process 1 fab = [[Intel]] | | process 1 fab = [[Intel]] | ||
| process 1 name = P1274 (CPU) / P1275 (SoC) | | process 1 name = P1274 (CPU) / P1275 (SoC) | ||
− | | process 1 date = | + | | process 1 date = 2017 |
| process 1 lith = 193 nm | | process 1 lith = 193 nm | ||
| process 1 immersion = Yes | | process 1 immersion = Yes | ||
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| process 2 volt = 0.70 V | | process 2 volt = 0.70 V | ||
| process 2 delta from = [[16 nm]] Δ | | process 2 delta from = [[16 nm]] Δ | ||
− | | process 2 fin pitch = | + | | process 2 fin pitch = |
− | | process 2 fin pitch Δ = | + | | process 2 fin pitch Δ = |
− | | process 2 fin width = | + | | process 2 fin width = |
| process 2 fin width Δ = | | process 2 fin width Δ = | ||
− | | process 2 fin height = | + | | process 2 fin height = |
− | | process 2 fin height Δ = | + | | process 2 fin height Δ = |
| process 2 gate len = | | process 2 gate len = | ||
| process 2 gate len Δ = | | process 2 gate len Δ = | ||
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<!-- Samsung --> | <!-- Samsung --> | ||
| process 3 fab = [[Samsung]] | | process 3 fab = [[Samsung]] | ||
− | | process 3 name = 10LPE<info>1<sup>st</sup> generation; 10 nm Low Power Early</info>, 10LPP<info>2<sup>nd</sup> generation; 10 nm Low Power | + | | process 3 name = 10LPE<info>1<sup>st</sup> generation; 10 nm Low Power Early</info>, 10LPP<info>2<sup>nd</sup> generation; 10 nm Low Power Performance</info>, 10LPU<info>3<sup>rd</sup> generation; 10 nm Low Power Ultimate</info> |
| process 3 date = April 2017 | | process 3 date = April 2017 | ||
| process 3 lith = 193 nm | | process 3 lith = 193 nm | ||
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| process 3 volt = 0.75 V | | process 3 volt = 0.75 V | ||
| process 3 delta from = [[14 nm]] Δ | | process 3 delta from = [[14 nm]] Δ | ||
− | | process 3 fin pitch = | + | | process 3 fin pitch = |
− | | process 3 fin pitch Δ = | + | | process 3 fin pitch Δ = |
| process 3 fin width = | | process 3 fin width = | ||
| process 3 fin width Δ = | | process 3 fin width Δ = | ||
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| process 3 cpp = 68 nm | | process 3 cpp = 68 nm | ||
| process 3 cpp Δ = 0.87x | | process 3 cpp Δ = 0.87x | ||
− | | process 3 mmp = | + | | process 3 mmp = 51 nm |
− | | process 3 mmp Δ = 0. | + | | process 3 mmp Δ = 0.80x |
| process 3 sram hp = 0.049 µm² | | process 3 sram hp = 0.049 µm² | ||
| process 3 sram hp Δ = 0.61x | | process 3 sram hp Δ = 0.61x | ||
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Intel's 10nm process is roughly 1.7x the raw logic density of the next densest 10nm process, albeit due to aggressive pattering techniques they also have the most complex process available to date. The process can support multiple threshold voltages, and features 12-metal interconnect layers with the bottom two made of cobalt. This is the first time cobalt is used in a high volume production node. Because of the ever shrinking geometries the wires get smaller each node. | Intel's 10nm process is roughly 1.7x the raw logic density of the next densest 10nm process, albeit due to aggressive pattering techniques they also have the most complex process available to date. The process can support multiple threshold voltages, and features 12-metal interconnect layers with the bottom two made of cobalt. This is the first time cobalt is used in a high volume production node. Because of the ever shrinking geometries the wires get smaller each node. | ||
− | + | At 10nm the wires become so small that the barrier layer takes up most of the interconnect, resulting in less space for the copper itself. As the cross section of the wire gets smaller the resistance rises exponentially. Cobalt aims to address this issue, it does not diffuse in the surrounding material, so the barrier layer can be reduced. And even though it has a higher resistance than copper in bulk, it has a two times lower resistance in very small wires. This can be attributed to the larger wires because of the reduced barrier layer and the larger grain size, witch reduces the electron scattering. It also has 10x better resistance to electron-migration. | |
− | At 10nm the wires become so small that the barrier layer takes up most of the interconnect, resulting in less space for the copper itself. As the cross section of the wire gets smaller the resistance rises exponentially. Cobalt aims to address this issue, it does not diffuse in the surrounding material, so the barrier layer can be reduced. And even though it has a higher resistance than copper in bulk, it has | ||
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− | + | Intel will leverage their initial 10nm process for their {{intel|Cannonlake|l=arch}}-based microprocessors which are used exclusively for mobile. They will then utilize their second generation, "10nm+" process, for {{intel|Icelake|l=arch}}-based processors which will be used for the mainstream and server platform. | |
{{clear}} | {{clear}} | ||
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=== Samsung === | === Samsung === | ||
[[File:ss 14-10nm.png|right|500px]] | [[File:ss 14-10nm.png|right|500px]] | ||
− | Samsung demonstrated their 128 | + | Samsung demonstrated their 128 Mebibit [[SRAM]] wafer from their 10nm FinFET process. Samsung, which unlike Intel uses LELELE (litho-etch-litho-etch-litho-etch), ramped up mass production in May of 2017. ChipWorks/TechInsight measured the CPP/MMP which came a little short of the Common Platform Alliance Paper which was presented in 2016, at 68 mm contacted gate pitch, 51 nm metal pitch, dual-depth [[shallow trench isolation]] (STI), and had single dummy gate. |
{| class="collapsible collapsed wikitable" | {| class="collapsible collapsed wikitable" | ||
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|} | |} | ||
− | Samsung's initial process was 10LPE (10 Low-Power Early) which was replaced by second generation evolved process 10LPP (10 Low-Power Plus). Samsung intends to introduce a third generational enhanced 10nm process called 8LPP (8 Low Power Plus) which will further improve performance and introduce a small density increase through cell enhancements | + | Samsung's initial process was 10LPE (10 Low-Power Early) which was replaced by second generation evolved process 10LPP (10 Low-Power Plus). Samsung intends to introduce a third generational enhanced 10nm process called 8LPP (8 Low Power Plus) which will further improve performance and introduce a small density increase through design rules and cell enhancements. 8LPP improvements over 10LPP is similar to their 11LPP improvements over their 14LPP. It's worth noting that Samsung intends 8LPP to be their last non-[[EVU]] node. All subsequent nodes will use EUV. |
=== TSMC === | === TSMC === | ||
− | TSMC reported a poly pitch of 64 nm with a metal pitch 42 nm. TechInsight measured them at 66 nm and 44 nm respectively. 10FF is the second process to use FinFET, and is the Industry's first use of Quad-Patterning. This allows for a full node shrink, enabling a 2X increase in logic density compared to their 16nm process. | + | TSMC reported a poly pitch of 64 nm with a metal pitch 42 nm. TechInsight measured them at 66 nm and 44 nm respectively. 10FF is the second process to use FinFET, and is the Industry's first use of Quad-Patterning. This allows for a full node shrink, enabling a 2X increase in logic density compared to their 16nm process. TSMC claims the 10FF process will have 15% higher performance while consuming 35% less power. |
{{clear}} | {{clear}} | ||
[[File:10nm tsmc.jpeg|200px]] | [[File:10nm tsmc.jpeg|200px]] | ||
== 10 nm Microprocessors== | == 10 nm Microprocessors== | ||
− | + | * Apple | |
− | {{ | + | ** {{apple|A10X}} |
− | + | ** {{apple|A11 Bionic}} | |
− | + | * HiSilicon | |
− | + | ** {{hisil|Kirin}} | |
− | + | * MediaTek | |
− | + | ** {{mediatek|Helio}} | |
− | + | * Qualcomm | |
− | + | ** {{qualcomm|Snapdragon 800}} | |
− | + | ** {{qualcomm|Centriq}} | |
− | + | * Xiaomi | |
− | + | ** {{xiaomi|Surge}} | |
− | }} | + | * Samsung |
+ | ** {{samsung|Exynos 9}} | ||
{{expand list}} | {{expand list}} | ||
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== 10 nm Microarchitectures== | == 10 nm Microarchitectures== | ||
* Intel | * Intel | ||
− | + | ** {{intel|Cannonlake|l=arch}} | |
− | + | ** {{intel|Icelake|l=arch}} | |
− | + | ** {{intel|Tigerlake|l=arch}} | |
− | + | ** {{intel|Sapphire Rapids|l=arch}} | |
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* Qualcomm | * Qualcomm | ||
** {{qualcomm|Falkor|l=arch}} | ** {{qualcomm|Falkor|l=arch}} | ||
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{{expand list}} | {{expand list}} | ||
== Documents == | == Documents == | ||
* [[:File:10-nm-technology-fact-sheet.pdf|Intel's 10 nm Technology: Delivering the Highest Logic Transistor Density in the Industry Through the Use of Hyper Scaling]] | * [[:File:10-nm-technology-fact-sheet.pdf|Intel's 10 nm Technology: Delivering the Highest Logic Transistor Density in the Industry Through the Use of Hyper Scaling]] | ||
− | * [[:File:Kaizad-Mistry-2017-Manufacturing.pdf|Intel | + | * [[:File:Kaizad-Mistry-2017-Manufacturing.pdf|Intel Technoogy & Manufacturing Day presentation, 10 nm]] |
− | * [[:File:Mark-Bohr-2017-Moores-Law.pdf|Intel | + | * [[:File:Mark-Bohr-2017-Moores-Law.pdf|Intel Technoogy & Manufacturing Day presentation, 10 nm / Moore's Law]] |
== References == | == References == | ||
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* Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016). | * Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016). | ||
* Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017. | * Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017. | ||
− | * Samsung's actual | + | * Samsung's actual transitor size was measured by ChipWorks/TechInsight based on the [[Qualcomm]] {{qualcomm|Snapdragon 835}} which is manufactured on Samsung's 10nm process. |
* [http://www.techinsights.com/technology-intelligence/overview/latest-reports/tsmc-10-nm-process/ TechInsights TSMC 10 nm Process Analysis] | * [http://www.techinsights.com/technology-intelligence/overview/latest-reports/tsmc-10-nm-process/ TechInsights TSMC 10 nm Process Analysis] | ||
− | [[ | + | [[Category:Lithography]] |