Editing cavium/octeon/cn3005-300bg350-scp (section)

== Datasheet ==
* [[:File:octeon cn30xx product brief.pdf|OCTEON CN30XX Processors Product Brief]]
base frequency	300 MHz (0.3 GHz, 300,000 kHz) +
core count	1 +
core name	cnMIPS +
designer	Cavium +
family	OCTEON +
first announced	January 30, 2006 +
first launched	May 1, 2006 +
full page name	cavium/octeon/cn3005-300bg350-scp +
has ecc memory support	false +
has hardware accelerators for cryptography	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	24 KiB (24,576 B, 0.0234 MiB) +
l1d$ description	64-way set associative +
l1d$ size	8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description	2-way set associative +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
l2$ description	2-way set associative +
l2$ size	0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
ldate	May 1, 2006 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory	2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth	0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN3005-300 SCP +
name	Cavium CN3005-300 SCP +
part number	CN3005-300BG350-SCP +
power dissipation	2 W (2,000 mW, 0.00268 hp, 0.002 kW) +
process	130 nm (0.13 μm, 1.3e-4 mm) +
release price	$ 19.00 (€ 17.10, £ 15.39, ¥ 1,963.27) +
series	CN3000 +
smp max ways	1 +
supported memory type	DDR2-533 +
technology	CMOS +
thread count	1 +
word size	64 bit (8 octets, 16 nibbles) +