Editing intel/microarchitectures/amber lake (section)

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[GCC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[LLVM]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code>
|}

=== CPUID ===
{| class="wikitable tc1 tc2 tc3 tc4 tc5"
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
|-
| rowspan="2" | {{intel|Amber Lake Y|Y|l=core}} || 0 || 0x6 || 0x8 || 0xE || 0x9
|-
| colspan="5" | Family 6 Model 142 Stepping 9
|}
codename	Amber Lake +
core count	2 +
designer	Intel +
first launched	April 2018 +
full page name	intel/microarchitectures/amber lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Amber Lake +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	14 nm (0.014 μm, 1.4e-5 mm) +