Editing amd/packages/socket am3 (section)

== Pin Map ==
:[[File:Socket AM3 pinmap.svg|800px]]

=== Socket AM2/AM2+/AM3 Differences ===
{|
!Pin!!Socket AM2||Socket AM2+||Socket AM3
|-
|AL4||RSVD||ALERT_L||ALERT_L
|-
|G5||RSVD||CORE_TYPE||CORE_TYPE
|-
|G20||MA1_CLK_H[1]||MA1_CLK_H[1]||MA_CLK_H[0]
|-
|G21||MA1_CLK_L[1]||MA1_CLK_L[1]||MA_CLK_L[0]
|-
|G19||MA0_CLK_H[1]||MA0_CLK_H[1]||MA_CLK_H[1]
|-
|H19||MA0_CLK_L[1]||MA0_CLK_L[1]||MA_CLK_L[1]
|-
|U24||RSVD||RSVD||MA_CLK_H[2]
|-
|V24||RSVD||RSVD||MA_CLK_L[2]
|-
|W26||RSVD||RSVD||MA_CLK_H[3]
|-
|W25||RSVD||RSVD||MA_CLK_L[3]
|-
|V27||MA1_CLK_H[0]||MA1_CLK_H[0]||MA_CLK_H[4]
|-
|W27||MA1_CLK_L[0]||MA1_CLK_L[0]||MA_CLK_L[4]
|-
|U27||MA0_CLK_H[0]||MA0_CLK_H[0]||MA_CLK_H[5]
|-
|U26||MA0_CLK_L[0]||MA0_CLK_L[0]||MA_CLK_L[5]
|-
|AE20||MA1_CLK_H[2]||MA1_CLK_H[2]||MA_CLK_H[6]
|-
|AE19||MA1_CLK_L[2]||MA1_CLK_L[2]||MA_CLK_L[6]
|-
|AG21||MA0_CLK_H[2]||MA0_CLK_H[2]||MA_CLK_H[7]
|-
|AG20||MA0_CLK_L[2]||MA0_CLK_L[2]||MA_CLK_L[7]
|-
|C19||MB1_CLK_H[1]||MB1_CLK_H[1]||MB_CLK_H[0]
|-
|D19||MB1_CLK_L[1]||MB1_CLK_L[1]||MB_CLK_L[0]
|-
|A18||MB0_CLK_H[1]||MB0_CLK_H[1]||MB_CLK_H[1]
|-
|A19||MB0_CLK_L[1]||MB0_CLK_L[1]||MB_CLK_L[1]
|-
|V31||RSVD||RSVD||MB_CLK_H[2]
|-
|W31||RSVD||RSVD||MB_CLK_L[2]
|-
|Y31||RSVD||RSVD||MB_CLK_H[3]
|-
|Y30||RSVD||RSVD||MB_CLK_L[3]
|-
|W29||MB1_CLK_H[0]||MB1_CLK_H[0]||MB_CLK_H[4]
|-
|W28||MB1_CLK_L[0]||MB1_CLK_L[0]||MB_CLK_L[4]
|-
|U31||MB0_CLK_H[0]||MB0_CLK_H[0]||MB_CLK_H[5]
|-
|U30||MB0_CLK_L[0]||MB0_CLK_L[0]||MB_CLK_L[5]
|-
|AL19||MB1_CLK_H[2]||MB1_CLK_H[2]||MB_CLK_H[6]
|-
|AL18||MB1_CLK_L[2]||MB1_CLK_L[2]||MB_CLK_L[6]
|-
|AJ19||MB0_CLK_H[2]||MB0_CLK_H[2]||MB_CLK_H[7]
|-
|AK19||MB0_CLK_L[2]||MB0_CLK_L[2]||MB_CLK_L[7]
|-
|W30||RSVD||RSVD||MA_EVENT_L
|-
|V29||RSVD||RSVD||MB_EVENT_L
|-
|AE28||RSVD||RSVD||MA0_ODT[1]
|-
|AE27||RSVD||RSVD||MA1_ODT[1]
|-
|AF31||RSVD||RSVD||MB0_ODT[1]
|-
|AG31||RSVD||RSVD||MB1_ODT[1]
|-
|E20||RSVD||RSVD||MA_RESET_L
|-
|B19||RSVD||RSVD||MB_RESET_L
|-
|F3||RSVD||RSVD||M_VDDIO_PWRGD
|-
|F2||RSVD||PLATFORM_TYPE
|-
|AK4||RSVD||SA[0]||SA[0]
|-
|E2||VID[1]||PVIEN/VID[1]||PVIEN/VID[1]
|-
|E3||VID[2]||SVD/VID[2]||SVD/VID[2]
|-
|C1||VID[3]||SVC/VID[3]||SVC/VID[3]
|-
|A4||VDD||VDDNB||VDDNB
|-
|A6||VDD||VDDNB||VDDNB
|-
|B5||VDD||VDDNB||VDDNB
|-
|B7||VDD||VDDNB||VDDNB
|-
|C6||VDD||VDDNB||VDDNB
|-
|C8||VDD||VDDNB||VDDNB
|-
|D7||VDD||VDDNB||VDDNB
|-
|D9||VDD||VDDNB||VDDNB
|-
|E10||VDD||VDDNB||VDDNB
|-
|E8||VDD||VDDNB||VDDNB
|-
|F11||VDD||VDDNB||VDDNB
|-
|F9||VDD||VDDNB||VDDNB
|-
|G10||VDD||VDDNB||VDDNB
|-
|G12||VDD||VDDNB||VDDNB
|-
|G4||RSVD||VDDNB_FB_H||VDDNB_FB_H
|-
|G3||RSVD||VDDNB_FB_L||VDDNB_FB_L
|-
|A12||VTT||VTT||VDDR
|-
|AG12||VTT||VTT||VDDR
|-
|AH12||VTT||VTT||VDDR
|-
|AJ12||VTT||VTT||VDDR
|-
|AK12||VTT||VTT||VDDR
|-
|AL12||VTT||VTT||VDDR
|-
|B12||VTT||VTT||VDDR
|-
|C12||VTT||VTT||VDDR
|-
|D12||VTT||VTT||VDDR
|-
|E12||VTT_SENSE||VTT_SENSE||VDDR_SENSE
|-
|B2||VOID||VOID||NP/RSVD
|-
|AE7||VOID||VOID||NP/VSS
|-
|H20||VOID||VOID||NP/VSS
|-
|AE9||VSS||VSS||VOID
|-
|H22||VSS||VSS||VOID
|}

=== Pin Description ===
{|
!Signal!!Description
|-
|ALERT_L||Programmable pin that can indicate different events, including a SB-TSI interrupt
|-
|CLKIN_H/L||200 MHz Differential PLL Reference Clock
|-
|CORE_TYPE||Indicates that the processor is capable of split core and northbridge voltage plane operation
|-
|CPU_PRESENT_L||Processor is present, shorted to VSS on the package
|-
|DBREQ_L, DBRDY||Debug Request/Ready
|-
|HTREF0, HTREF1||HyperTransport Compensation Resistor to VSS, VLDT
|-
|L0_CADIN/OUT_H/L[15:0]||HT Link 0 Differential Command/Address/Data Input/Output
|-
|L0_CLKIN/OUT_H/L[1:0]||HT Link 0 Differential Clock Input/Output
|-
|L0_CTLIN_H/L[1:0]||HT Link 0 Differential Control Input/Output
|-
|LDTSTOP_L||HT Stop Control Input for power management and link width and frequency change
|-
|MA/MB_ADD[15:0]||DRAM Column/Row Address
|-
|MA/MB_BANK[2:0]||DRAM Bank Address
|-
|MA/MB_CAS_L||DRAM Column Address Strobe
|-
|MA/MB_CHECK[7:0]||DRAM ECC Bits
|-
|MA/MB_CKE[1:0]||DRAM Clock Enable
|-
|MA/MB_CLK_H/L[7:0]||DRAM Differential Clock
|-
|MA/MB_DATA[63:0]||DRAM Data Bus
|-
|MA/MB_DM[8:0]||DRAM Data Mask
|-
|MA/MB_DQS_H/L[8:0]||DRAM Differential Data Strobe
|-
|MA/MB_EVENT_L||DRAM Thermal Event Status
|-
|MA/MB_RAS_L||DRAM Row Address Strobe
|-
|MA/MB_RESET_L||DRAM Reset Pin for Suspend-to-RAM Power Management Mode
|-
|MA/MB_WE_L||DRAM Write Enable
|-
|MA0/MA1/MB0/MB1_CS_L[1:0]||DRAM Chip Select
|-
|MA0/MA1/MB0/MB1_ODT[1:0]||DRAM Enable Pin for On Die Termination
|-
|M_VDDIO_PWRGD||Not supported
|-
|M_VREF||DRAM Interface Voltage Reference
|-
|M_ZP, M_ZN||Compensation Resistor to VSS, VDDIO
|-
|NP/RSVD||Pin is not populated on OPGA-938 and OPGA-940 package, unconnected on Socket AM3
|-
|NP/VSS||Pin is not populated on OPGA-938 package, connected to ground on OPGA-940 and Socket AM3
|-
|PROCHOT_L||Processor in HTC-active state input/output
|-
|PSI_L||Power Status Indicator (low power state) for VDD regulator
|-
|PVIEN/VID[1]||Prior to PWROK assertion signals to the processor whether the platform supports PVI or SVI operation
|-
|PWROK||Voltages and CLKIN have reached specified operation
|-
|RESET_L||Processor Reset
|-
|RSVD||Reserved
|-
|SA[0]||Sideband interface (APML/SBI/SMBus) address selection
|-
|SIC, SID||Sideband Temperature Sensor Interface Clock/Data
|-
|SVC/VID[3]||Serial VID Interface Clock
|-
|SVD/VID[2]||Serial VID Interface Data
|-
|TCK, TDI, TDO, TMS, TRST_L||JTAG interface
|-
|TEST*||Test signal
|-
|THERMDA, THERMDC||Thermal Diode Anode, Cathode
|-
|THERMTRIP_L||Thermal Sensor Trip output
|-
|VDDA||Filtered PLL supply voltage
|-
|VDDIO||DRAM I/O ring power supply
|-
|VDDIO_FB_H/L||Differential feedback to VDDIO regulator
|-
|VDDNB||Northbridge power supply
|-
|VDDNB_FB_H/L||Differential feedback to VDDNB regulator
|-
|VDDR||VDDR power supply
|-
|VDDR_SENSE||VDDR voltage monitor pin
|-
|VDD||Core power supply
|-
|VDD_FB_H/L||Differential feedback to VDD regulator
|-
|VID[5:0]||Voltage ID (PVI) for VDD regulator
|-
|VLDT_A/B||HyperTransport I/O ring power supply
|-
|VOID||Missing pins and pin holes for mechanical keying
|-
|VSS||Ground
|}
designer	AMD +
first launched	February 9, 2009 +
instance of	package +
market segment	Desktop +
microarchitecture	K10 +
name	Socket AM3 +
package	OPGA-938 +
package contacts	938 +
package length	40 mm (4 cm, 1.575 in) +
package pitch	1.27 mm (0.05 in) +
package type	Organic Micro Pin Grid Array +
package width	40 mm (4 cm, 1.575 in) +
socket	Socket AM3 +
tdp	125 W (125,000 mW, 0.168 hp, 0.125 kW) +