Editing nvidia/microarchitectures/denver (section)

== Cache ==

For two cores of Denver total cache size is:

{{cache size
|l1 cache=384 KiB
|l1i cache=256 KiB
|l1i break=2x128 KiB
|l1i desc=4-way set associative
|l1d cache=128KiB
|l1d break=2x64 KiB
|l1d desc=4-way set associative
|l2 cache=2 MiB
|l2 break=1x2 MiB
|l2 desc=16-way set associative
}}

L1i TLB has 128 entries for 4 KiB pages and is 4-way set-associative.
L1d TLB has 280 entries and supports 4 KiB, 64 KiB, 1 MiB and 2 MiB pages.
TLB walk is accelerated by L2 TLB of 2048 entries in 4-way set-associative buffer.
codename	Denver +
core count	2 +
designer	Nvidia +
first launched	2014 +
full page name	nvidia/microarchitectures/denver +
instance of	microarchitecture +
instruction set architecture	ARMv8 +
l1$ size	384 KiB (393,216 B, 0.375 MiB) +
l1d$ description	4-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	4-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	16-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Denver +
process	28 nm (0.028 μm, 2.8e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +