Editing ambric/am2000/am2035 (section)

== Memory controller ==
{{integrated memory controller
| type               = DDR2-400
| controllers        = 2
| channels           = 1
| ecc support        = 
| max bandwidth      = 
| bandwidth schan    = 
| bandwidth dchan    = 
| max memory         = 4 GiB
}}
base frequency	333 MHz (0.333 GHz, 333,000 kHz) +
bus speed	100 MHz (0.1 GHz, 100,000 kHz) +
clock multiplier	3.3 +
core count	280 +
designer	Ambric +
family	Am2000 +
first announced	October 10, 2006 +
first launched	January 2007 +
full page name	ambric/am2000/am2035 +
has feature	PCIe +, JTAG +, GPIO + and serial flash +
has locked clock multiplier	false +
instance of	microprocessor +
last order	2012 +
last shipment	2012 +
ldate	January 2007 +
market segment	Embedded +
max memory	4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
microarchitecture	Ambric +
model number	Am2035 +
name	Am2035 +
part number	Am2035 +
process	130 nm (0.13 μm, 1.3e-4 mm) +
series	Gen 1 +
technology	CMOS +
word size	32 bit (4 octets, 8 nibbles) +