Editing amd/microarchitectures/zen 2 (section)

== Rome ==
{{amd|Rome|l=core}} is codename for AMD's server chip based on the Zen 2 core. Like prior generation ({{amd|Naples|l=core}}), Rome utilizes a [[chiplet]] multi-chip package design. Each chip comprises of nine [[dies]] - one centralized I/O die and eight compute dies. The compute dies are fabricated on [[TSMC]]'s [[7 nm process]] in order to take advantage of the lower power and [[transistor density|higher density]]. On the other hand, the I/O makes use of [[GlobalFoundries]] mature [[14 nm process]].

The centralized I/O die incorporates eight {{amd|Infinity Fabric}} links, 128 [[PCIe]] Gen 4 lanes, and eight [[DDR4]] memory channels. The full capabilities of the I/O have not been disclosed yet. Attached to the I/O die are eight compute dies - each with eight Zen 2 core - for a total of 64 cores and 128 threads per chip.
codename	Zen 2 +
core count	4 +, 6 +, 8 +, 12 +, 16 +, 24 +, 32 + and 64 +
designer	AMD +
first launched	July 2019 +
full page name	amd/microarchitectures/zen 2 +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	TSMC + and GlobalFoundries +
microarchitecture type	CPU +
name	Zen 2 +
pipeline stages	19 +