Editing nervana/nnp/nnp-t 1400 (section)

== Cache ==
{{main|nervana/microarchitectures/spring_crest#Memory_Hierarchy|l1=Spring Crest § Cache}}
* 60 MiB of tightly-coupled scratchpad memory
** 24 x 2.5 MiB/core
back image	+
base frequency	1,100 MHz (1.1 GHz, 1,100,000 kHz) +
core count	24 +
designer	Intel +
die area	680 mm² (1.054 in², 6.8 cm², 680,000,000 µm²) +
family	NNP +
first announced	November 12, 2019 +
first launched	November 12, 2019 +
full page name	nervana/nnp/nnp-t 1400 +
has ecc memory support	true +
instance of	microprocessor +
ldate	November 12, 2019 +
main image	+
main image caption	NPU with 4 HBM2 stacks +
manufacturer	TSMC +
market segment	Server +
max memory	32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) +
max memory bandwidth	1,144.409 GiB/s (1,171,875 MiB/s, 1,228.8 GB/s, 1,228,800 MB/s, 1.118 TiB/s, 1.229 TB/s) +
max memory channels	32 +
microarchitecture	Spring Crest +
model number	NNP-T 1400 +
name	NNP-T 1400 +
package	FCBGA-3325 +
peak flops (half-precision)	108,000,000,000,000 FLOPS (108,000,000,000 KFLOPS, 108,000,000 MFLOPS, 108,000 GFLOPS, 108 TFLOPS, 0.108 PFLOPS, 1.08e-4 EFLOPS, 1.08e-7 ZFLOPS) +
power dissipation	175 W (175,000 mW, 0.235 hp, 0.175 kW) +
process	16 nm (0.016 μm, 1.6e-5 mm) +
series	NNP-T +
smp interconnect	InterChip Link +
smp interconnect links	16 +
smp interconnect rate	28 GT/s +
supported memory type	HBM2-2400 +
tdp	375 W (375,000 mW, 0.503 hp, 0.375 kW) +
technology	CMOS +
transistor count	27,000,000,000 +