Editing nervana/nnp (section)

=== Codenames ===
{| class="wikitable"
|-
! Introduction || Type || Microarchitecture || Process
|-
| 2017<sup>1</sup> || [[Training]] || {{nervana|Lake Crest|l=arch}} || [[TSMC 28 nm|28 nm]]
|-
| 2019 || Training || {{nervana|Spring Crest|l=arch}} || [[TSMC 16 nm|16 nm]]
|-
| 2019 || [[Inference]] || {{nervana|Spring Hill|l=arch}} || [[Intel 10 nm|10 nm]]
|- style="text-decoration:line-through"
| 2020 || Training+CPU || {{nervana|Knights Crest|l=arch}} || ?
|}

1 - Only sampled
designer	Intel +
first announced	May 23, 2018 +
first launched	2019 +
full page name	nervana/nnp +
instance of	integrated circuit family +
main designer	Intel +
manufacturer	Intel + and TSMC +
name	NNP +
package	PCIe x16 Gen 3 Card +, OCP OAM + and M.2 +
process	28 nm (0.028 μm, 2.8e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) +
technology	CMOS +