Editing cavium/octeon/cn3630-500bg1521-scp (section)

== Memory controller ==
{{memory controller
|type=DDR2-800
|ecc=Yes
|max mem=16 GiB
|controllers=1
|channels=1
|width=64 bit
|max bandwidth=5.96 GiB/s
|bandwidth schan=5.96 GiB/s
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN3630-500 SCP - Cavium#package +
base frequency	500 MHz (0.5 GHz, 500,000 kHz) +
core count	4 +
core name	cnMIPS +
designer	Cavium +
family	OCTEON +
first announced	August 2005 +
first launched	August 2005 +
full page name	cavium/octeon/cn3630-500bg1521-scp +
has ecc memory support	true +
has hardware accelerators for cryptography	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	160 KiB (163,840 B, 0.156 MiB) +
l1d$ description	64-way set associative +
l1d$ size	32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description	64-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	8-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldate	August 2005 +
main image	+
manufacturer	TSMC +
market segment	Networking +
max cpu count	1 +
max memory	16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth	5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN3630-500 SCP +
name	Cavium CN3630-500 SCP +
package	FCBGA-1521 +
part number	CN3630-500BG1521-SCP +
process	130 nm (0.13 μm, 1.3e-4 mm) +
series	CN3600 +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	4 +
word size	64 bit (8 octets, 16 nibbles) +