Editing marvell/armada/628 (section)

== Cache ==
{{main|intel/microarchitectures/sheeva pj4#Memory_Hierarchy|l1=Sheeva PJ4 § Cache}}
{{cache size
|l1 cache=192 KiB
|l1i cache=96 KiB
|l1i break=3x32 KiB
|l1d cache=96 KiB
|l1d break=3x32 KiB
|l2 cache=1 MiB
|l2 break=1x1 MiB
}}
base frequency	1,500 MHz (1.5 GHz, 1,500,000 kHz) + and 624 MHz (0.624 GHz, 624,000 kHz) +
core count	3 +
core name	Sheeva PJ4 +
designer	Marvell +
family	ARMADA 600 +
first announced	September 23, 2010 +
first launched	March 2011 +
full page name	marvell/armada/628 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	GC1000 +
integrated gpu base frequency	500 MHz (0.5 GHz, 500,000 KHz) +
integrated gpu designer	Vivante +
io voltage	1.5 V (15 dV, 150 cV, 1,500 mV) +, 3 V (30 dV, 300 cV, 3,000 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
io voltage tolerance	0.3 V +
isa	ARMv6 + and ARMv5 +
isa family	ARM +
l1$ size	192 KiB (196,608 B, 0.188 MiB) +
l1d$ size	96 KiB (98,304 B, 0.0938 MiB) +
l1i$ size	96 KiB (98,304 B, 0.0938 MiB) +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	March 2011 +
main image	+
manufacturer	TSMC +
market segment	Mobile +
max cpu count	1 +
max memory bandwidth	7.942 GiB/s (8,132.608 MiB/s, 8.528 GB/s, 8,527.658 MB/s, 0.00776 TiB/s, 0.00853 TB/s) +
max memory channels	1 +
microarchitecture	Sheeva PJ4 +
model number	628 +
name	ARMADA 628 +
part number	88AP628 +
platform	ARMADA +
process	55 nm (0.055 μm, 5.5e-5 mm) +
series	600 +
smp max ways	1 +
supported memory type	DDR3-1066 + and DDR2-800 +
thread count	3 +
word size	32 bit (4 octets, 8 nibbles) +