Editing intel/core i3/i3-380m (section)

== Cache ==
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}}
{{cache size
|l1 cache=128 KiB
|l1i cache=64 KiB
|l1i break=2x32 KiB
|l1i desc=4-way set associative
|l1i policy=write-back
|l1d cache=64 KiB
|l1d break=2x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=512 KiB
|l2 break=2x256 KiB
|l2 desc=8-way set associative
|l2 policy=write-back
|l3 cache=3 MiB
|l3 break=2x1.5 MiB
|l3 desc=12-way set associative
|l3 policy=write-back
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Core i3-380M - Intel#package + and Core i3-380M - Intel#io +
base frequency	2,533.33 MHz (2.533 GHz, 2,533,330 kHz) +
bus links	1 +
bus rate	2,500 MT/s (2.5 GT/s, 2,500,000 kT/s) +
bus type	DMI 1.0 +
chipset	Ibex Peak +
clock multiplier	19 +
core count	2 +
core family	6 +
core model	37 +
core name	Arrandale +
core stepping	K0 +
cpuid	0x20655 +
designer	Intel +
device id	0x0046 +
die area	81 mm² (0.126 in², 0.81 cm², 81,000,000 µm²) +
family	Core i3 +
first announced	September 26, 2010 +
first launched	September 26, 2010 +
full page name	intel/core i3/i3-380m +
has ecc memory support	false +
has extended page tables support	true +
has feature	Enhanced SpeedStep Technology +, Extended Page Tables +, Flex Memory Access +, Hyper-Threading Technology + and Intel VT-x +
has intel enhanced speedstep technology	true +
has intel flex memory access support	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
instance of	microprocessor +
integrated gpu	HD Graphics (Ironlake) +
integrated gpu base frequency	500 MHz (0.5 GHz, 500,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	12 +
integrated gpu max frequency	667 MHz (0.667 GHz, 667,000 KHz) +
isa	x86-64 +
isa family	x86 +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	4-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	8-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description	12-way set associative +
l3$ size	3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
ldate	September 26, 2010 +
manufacturer	Intel +
market segment	Mobile +
max cpu count	1 +
max junction temperature	378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory	8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max memory bandwidth	15.88 GiB/s (16,261.12 MiB/s, 17.051 GB/s, 17,051.02 MB/s, 0.0155 TiB/s, 0.0171 TB/s) +
max memory channels	2 +
max pcie lanes	16 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Westmere +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	i3-380M +
name	Intel Core i3-380M +
package	rPGA-988A +
part number	CP80617004116AH +
platform	Calpella +
process	32 nm (0.032 μm, 3.2e-5 mm) +
s-spec	SLBZX +
series	i3-300 +
smp max ways	1 +
supported memory type	DDR3-1066 +
tdp	35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technology	CMOS +
thread count	4 +
transistor count	382,000,000 +
word size	64 bit (8 octets, 16 nibbles) +