Editing intel/chipsets/poulsbo (section)

==Overview ==
[[File:Poulsbo lrg and sm.png|thumb|right|Comparison between the two Poulsbo packages.]]
The Poulsbo chipset, part of the {{intel|Menlow|l=platform}}, offers the memory controller along with the much of the southbridge. Unlike all previous [[front-side bus]] signaling logic which used [[gunning transceiver logic|GTL]], to allow for more power saving, Poulsbo became the first chipset to support CMOS signaling as well. Such functionality was only offered by the {{intel|Silverthorne|l=core}}-based processors. In 2009 Intel released a second variant of Poulsbo in a larger [[package]].
bus speed	533 MHz (0.533 GHz, 533,000 kHz) +
bus type	FSB +
designer	Intel + and Imagination Technologies +
first announced	April 18, 2007 +
first launched	March 2, 2008 +
instance of	chipset +
manufacturer	Intel +
name	Poulsbo +
process	130 nm (0.13 μm, 1.3e-4 mm) +
technology	CMOS + and GTL +