Editing hisilicon/kunpeng/920-3226 (section)

== Cache ==
{{main|hisilicon/microarchitectures/taishan_v110#Memory_Hierarchy|l1=TaiShan v110 § Cache}}
{{cache size
|l1 cache=4 MiB
|l1i cache=2 MiB
|l1i break=32x64 KiB
|l1d cache=2 MiB
|l1d break=32x64 KiB
|l2 cache=16 MiB
|l2 break=32x512 KiB
|l3 cache=32 MiB
|l3 break=32x1 MiB
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Kunpeng 920-3226 - HiSilicon#pcie +
base frequency	2,600 MHz (2.6 GHz, 2,600,000 kHz) +
core count	32 +
core name	TaiShan v110 +
designer	HiSilicon + and ARM Holdings +
die count	3 +
family	Hi16xx +
first announced	April 26, 2019 +
first launched	April 26, 2019 +
full page name	hisilicon/kunpeng/920-3226 +
has ecc memory support	true +
instance of	microprocessor +
is multi-chip package	true +
isa	ARMv8.2 +
isa family	ARM +
l1$ size	4,096 KiB (4,194,304 B, 4 MiB) +
l1d$ size	2,048 KiB (2,097,152 B, 2 MiB) +
l1i$ size	2,048 KiB (2,097,152 B, 2 MiB) +
l2$ size	16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ size	32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldate	April 26, 2019 +
main image	+
manufacturer	TSMC +
market segment	Server +
max cpu count	4 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels	8 +
max sata ports	2 +
max usb ports	4 +
microarchitecture	TaiShan v110 +
model number	920-3226 +
name	Kunpeng 920-3226 +
series	920 +
smp max ways	4 +
supported memory type	DDR4-2933 +
tdp	120 W (120,000 mW, 0.161 hp, 0.12 kW) +
technology	CMOS +
thread count	32 +
transistor count	20,000,000,000 +
used by	HiSilicon D06 +, TaiShan 5280 +, TaiShan 5290 + and TaiShan X6000 +
word size	64 bit (8 octets, 16 nibbles) +