-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Editing fujitsu/sparc64/sparc64 xii (section)
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Retrieved from "https://en.wikichip.org/wiki/fujitsu/sparc64/sparc64_xii"
Facts about "SPARC64 XII - Fujitsu"
base frequency | 4,250 MHz (4.25 GHz, 4,250,000 kHz) + |
core count | 12 + |
designer | Fujitsu + |
family | SPARC64 + |
first announced | 2015 + |
first launched | April 4, 2017 + |
full page name | fujitsu/sparc64/sparc64 xii + |
instance of | microprocessor + |
isa | SPARC V9 + |
isa family | SPARC + |
ldate | April 4, 2017 + |
main image | + |
main image caption | SPARC64 XII Chip + |
manufacturer | TSMC + |
market segment | Server + |
max cpu count | 32 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
microarchitecture | SPARC64 XII + |
model number | SPARC64 XII + |
name | SPARC64 XII + |
process | 20 nm (0.02 μm, 2.0e-5 mm) + |
smp max ways | 32 + |
technology | CMOS + |
thread count | 96 + |
word size | 64 bit (8 octets, 16 nibbles) + |