Editing amd/epyc/7261 (section)

== Cache ==
{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}
{{cache size
|l1 cache=768 KiB
|l1i cache=512 KiB
|l1i break=8x64 KiB
|l1i desc=4-way set associative
|l1d cache=256 KiB
|l1d break=8x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=4 MiB
|l2 break=8x512 KiB
|l2 desc=8-way set associative
|l2 policy=write-back
|l3 cache=64 MiB
|l3 break=8x8 MiB
|l3 desc=16-way set associative
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7261 - AMD#io +
base frequency	2,500 MHz (2.5 GHz, 2,500,000 kHz) +
clock multiplier	25 +
core count	8 +
core family	23 +
core model	1 +
core name	Naples +
core stepping	B2 +
designer	AMD +
die area	213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count	4 +
family	EPYC +
first announced	June 14, 2018 +
first launched	June 14, 2018 +
full page name	amd/epyc/7261 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multiplier	false +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	8-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	4-way set associative +
l1i$ size	512 KiB (524,288 B, 0.5 MiB) +
l2$ description	8-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description	16-way set associative +
l3$ size	64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldate	June 14, 2018 +
manufacturer	GlobalFoundries +
market segment	Server +
max cpu count	2 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels	8 +
max pcie lanes	128 +
microarchitecture	Zen +
model number	7261 +
name	EPYC 7261 +
package	FCLGA-4094 + and SP3 +
part number	PS7261BEV8RAF +
process	14 nm (0.014 μm, 1.4e-5 mm) +
series	7000 +
smp max ways	2 +
socket	SP3 + and LGA-4094 +
supported memory type	DDR4-2666 + and DDR4-2400 +
tdp	155 W (155,000 mW, 0.208 hp, 0.155 kW) + and 170 W (170,000 mW, 0.228 hp, 0.17 kW) +
technology	CMOS +
thread count	16 +
transistor count	19,200,000,000 +
turbo frequency (1 core)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (2 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (3 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (4 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (5 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (6 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (7 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (8 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +