Editing cavium/octeon/cn3120-550bg868-scp

{{cavium title|CN3120-550 SCP}}
{{chip
| name                = Cavium CN3120-550 SCP
| no image            = 
| image               = octeon cn31xx.png
| image size          = 
| caption             = 
| designer            = Cavium
| manufacturer        = TSMC
| model number        = CN3120-550 SCP
| part number         = CN3120-550BG868-SCP
| part number 2       = 
| part number 3       = 
| part number 4       = 
| market              = Embedded
| first announced     = January 30, 2006 
| first launched      = May 1, 2006
| last order          = 
| last shipment       = 
| release price       = $125.00

| family              = OCTEON
| series              = CN3100
| locked              = 
| frequency           = 550 MHz
| bus type            = 
| bus speed           = 
| bus rate            = 
| bus links           = 
| clock multiplier    = 

| isa family          = MIPS
| isa                 = MIPS64
| microarch           = cnMIPS
| platform            = 
| chipset             = 
| core name           = cnMIPS
| core family         = 
| core model          = 
| core stepping       = 
| process             = 130 nm
| transistors         = 
| technology          = CMOS
| die area            = <!-- XX mm² -->
| die width           = 
| die length          = 
| word size           = 64 bit
| core count          = 2
| thread count        = 2
| max cpus            = 1
| max memory          = 4 GiB
| max memory addr     = 


| power               = 7 W
| v core              = 
| v core tolerance    = 
| v io                = 
| v io tolerance      = 
| v io 2              = 
| v io 3              = 
| sdp                 = 
| tdp                 = 
| tdp typical         = 
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = 
| temp max            = 
| tjunc min           = <!-- .. °C -->
| tjunc max           = 
| tcase min           = 
| tcase max           = 
| tstorage min        = 
| tstorage max        = 
| tambient min        = 
| tambient max        = 

|package module 1={{packages/cavium/hsbga-868}}
}}
The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

== Cache ==
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
{{cache size
|l1 cache=80 KiB
|l1i cache=64 KiB
|l1i break=2x32 KiB
|l1i desc=4-way set associative
|l1d cache=16 KiB
|l1d break=2x8 KiB
|l1d desc=64-way set associative
|l1d policy=Write-through
|l2 cache=256 KiB
|l2 break=1x128 KiB
|l2 desc=8-way set associative
}}

== Memory controller ==
{{memory controller
|type=DDR2-667
|ecc=Yes
|max mem=4 GiB
|controllers=1
|channels=1
|width=64 bit
|max bandwidth=4.97 GiB/s
|bandwidth schan=4.97 GiB/s
}}

Optional low-latency controller for content-based processing and meta data

{{memory controller
|type=DDR2-667
|ecc=Yes
|max mem=2 GiB
|controllers=1
|channels=1
|width=16 bit
|max bandwidth=1.24 GiB/s
|bandwidth schan=1.24 GiB/s
}}

== Expansions ==
{{expansions
|pcix width=32 bit
|pcix clock=100 MHz
|pcix rate=381.5 MiB/s
|pci extra=host or slave
|usb revision=2.0
|usb ports=1
|usb rate=60 MB/s
|usb extra=host / PHY
|uart=yes
|uart ports=2
|gp io=Yes
}}

== Networking ==
{{network
|mii opts=Yes
|rgmii=yes
|rgmii ports=3
|gmii=yes
|gmii ports=1
|pcm=Yes
}}

== Hardware Accelerators ==
{{accelerators
|encryption=Yes
|encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
|tcp=Yes
|qos=Yes
}}

== Block diagram ==
[[File:octeon cn31xx block diagram.png|750px]]

== Datasheet ==
* [[:File:octeon cn31xx product brief.pdf|OCTEON CN31XX Single- and Dual-Core Product Brief]]
back image	File:jiqwpmvjwk +
bus type	wszsqjsnqo +
chipset	mjfcyhnfad +, bcftfdnkbb +, cpiasrjllg + and ojavuayrck +
core family	rgqshlmpmn +, yyfimhytwh +, xyojigaqvn + and jcvobqrgqn +
core model	gspaqkrtqg +, ohhvdjfqmd +, kykccozvad + and sdhmrvooqn +
core name	gplexnjuow +, ecsionotss +, dflnfbmtub + and aczukmurnn +
core stepping	kfvpcfepbn +, uudknduxqo +, jdyfkytsde + and gdwhnvhtvp +
core voltage tolerance	yestjyzyuc +
cpuid	krsaxfljgu +, rjpvlrbdnm +, ygizksqspm + and tgsbfzstbn +
designer	+1 213 425 1453 +, vqkqselnmp +, rqylglopuy +, vfuqofhrts + and fnpgoerzre +
family	zzvnpfzcfp + and dpvnjpqlan +
full page name	cavium/octeon/cn3120-550bg868-scp +
has ecc memory support	true +
has hardware accelerators for cryptography	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
io voltage tolerance	dqvftyconu +
isa	iwnvhjjkbw + and mwjrmyawrm +
isa family	ndjfslrlhv + and daeenzqwxg +
l1$ size	80 KiB (81,920 B, 0.0781 MiB) +
l1d$ description	64-way set associative +
l1d$ size	16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description	4-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	8-way set associative +
l2$ size	0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
main image	File:lrbhdfegjh +
main image caption	qoobuadeqq +
manufacturer	+1 213 425 1453 +, vbgfqmzodj +, pzzbazuplx +, nftbnoqnnz + and cxctmemudp +
market segment	osxiwbulzt +, fbrpciztmy + and nlnpdyeijz +
max dts temperature	trthaiesax +
max memory address	redirect-f1a83ae7b063638e256582101b43cc67@webmark.eting.org +
max memory bandwidth	4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels	1 +
max operating temperature	oqgaifivno +
microarchitecture	qvjhjirlrh +, uptasoyfyc +, iixxoitiaz + and yebdhobuhk +
min dts temperature	ahdkkrxqow +
min operating temperature	oadnoitbsk +
model number	ptsxhheyaj +
name	xjqsvbpjlz +
neuron count	tfatjildcu +
part number	pbctgrrrzc +, vsyxxqhtfw +, cwzwqijwvy +, amhzaxqxgt +, nasbhkeiou +, ldkifcropf +, pqnqvsdvzg +, qdsrrsnksy +, ractiyjxrx + and zvvtgnwtsj +
platform	rvwqdbleur +
s-spec	kbnfaewrhd +, jlumdkmcpk +, krtieuddaf +, xhbxxasynn +, kexxjzrzaa +, zuvsefcavu +, rkgsqoctnn +, uovqripsjg +, rzbipocvzl +, ltnijnifyq +, xwjufdmnvu + and mmvuxsmdit +
s-spec (qs)	dkjcehebok +, ncglyeneje +, yzkvalrmav +, evblsdjvck +, iieqlmhmys +, kpmhdsytub +, kwmjmjyoqw +, dwnoqkecbr +, dnpxsgszgm +, shtsngtmei +, deqmtodxce + and tykbvngdzd +
series	lsjggnltxh +
smp interconnect	fdzpleodcg +
smp interconnect links	omaplnwvjo +
smp interconnect rate	wycwjvlyqq +
smp max ways	cijchrokwv +
supported memory type	DDR2-667 +
synapse count	cdqzxiklvk +
turbo frequency (17 cores)	hlmfsukidp +
turbo frequency (18 cores)	pmzicxezoj +
turbo frequency (19 cores)	yfaguqerhf +
turbo frequency (20 cores)	rblcvdcgvs +
turbo frequency (21 cores)	phucamoben +
turbo frequency (22 cores)	evromxcyki +
turbo frequency (23 cores)	jrvzvtkece +
turbo frequency (24 cores)	yqdxqaantq +
turbo frequency (25 cores)	gljtvfkdnn +
turbo frequency (26 cores)	ahkodvfmnj +
turbo frequency (27 cores)	vxvwzzmyfx +
turbo frequency (28 cores)	lzvqnszlil +
turbo frequency (29 cores)	lintkquhfe +
turbo frequency (30 cores)	xjekaggrak +
turbo frequency (31 cores)	evdmcrbwsr +
turbo frequency (32 cores)	tyytgbhspx +