Editing intel/microarchitectures/cooper lake

{{intel title|Cooper Lake|arch}}
{{microarchitecture
|atype=CPU
|name=Cooper Lake
|designer=Intel
|manufacturer=Intel
|introduction=2019
|process=14 nm
|type=Superscalar
|oooe=Yes
|speculative=Yes
|renaming=Yes
|stages min=14
|stages max=19
|isa=x86-64
|extension=MOVBE
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AVX
|extension 11=AVX2
|extension 12=AES
|extension 13=PCLMUL
|extension 14=FSGSBASE
|extension 15=RDRND
|extension 16=FMA3
|extension 17=F16C
|extension 18=BMI
|extension 19=BMI2
|extension 20=VT-x
|extension 21=VT-d
|extension 22=TXT
|extension 23=TSX
|extension 24=RDSEED
|extension 25=ADCX
|extension 26=PREFETCHW
|extension 27=CLFLUSHOPT
|extension 28=XSAVE
|extension 29=SGX
|extension 30=MPX
|extension 31=AVX-512
|l1i=32 KiB
|l1i per=core
|l1i desc=8-way set associative
|l1d=32 KiB
|l1d per=core
|l1d desc=8-way set associative
|l2=1 MiB
|l2 per=core
|l2 desc=16-way set associative
|l3=1.375 MiB
|l3 per=core
|l3 desc=11-way set associative
|core name=Cooper Lake X
|core name 2=Cooper Lake SP
|core name 3=Cooper Lake AP
|predecessor=Cascade Lake
|predecessor link=intel/microarchitectures/cascade lake
|successor=Ice Lake (Server)
|successor link=intel/microarchitectures/ice lake (server)
|contemporary=Coffee Lake
|contemporary link=intel/microarchitectures/coffee lake
}}
'''Cooper Lake''' ('''CPL''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers. Though announced to be releasing in 1H2020 for all segments, Intel said that, in an effort to streamline their product portfolio, the mainstream version (based on the {{intel|Whitley|l=platform}}) is going to be scrapped and just the {{intel|Cedar Island|l=platform}} chips are going to be released. These are chips that range from 28 to 56 cores, primarily targeted at niche AI and HPC workloads, hence the bfloat16 ([[brain floating-point format]]) support.

For scalable server class processors, Intel branded it as {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}.


== Codenames ==
{| class="wikitable"
|-
! Core !! Abbrev !! Target
|-
| {{intel|Cooper Lake X|l=core}} || CPL-X || High-end desktops & enthusiasts market
|-
| {{intel|Cooper Lake W|l=core}} || CPL-W || Enterprise/Business workstations
|-
| {{intel|Cooper Lake SP|l=core}} || CPL-SP || Server Scalable Processors
|-
| {{intel|Cooper Lake AP|l=core}} || CPL-AP || Server Advanced Processors
|}

== Brands ==
{{empty section}}

== Release Dates ==
[[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|Cooper Lake and {{\\|Ice Lake}} roadmap.]]
Cooper Lake is expected to be released in the first half of 2020.

== Process Technology ==
Cooper Lake is fabricated on Intel's 3rd generation enhanced [[14 nm process|14nm++ process]].

== Architecture ==
Cooper Lake is based on the {{intel|Whitley|l=platform}} platform.
=== Key changes from {{\\|Cascade Lake}} ===

{{future information}}

* SoC
** Mainstream 56 cores (up from 28) (note that {{intel|Cascade Lake AP|l=core}} already offered up to 56 cores)
*** Socketed (from soldered and only sold as part of the S9200WK module)
** 3-die multi-chip package (up from a single monolithic die)
* Memory
** Higher bandwidth (174.84 GiB/s, up from 119.209 GiB/s)
** Octa-channel (up from hexa-channel) 
** Optane DC DIMMs
*** Apache Pass '''→''' Barlow Pass
* Platform
** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}} (mainstream)
** {{intel|Walker Pass|l=platform}} '''→''' {{intel|Cedar Island|l=platform}} (AP)
* Packaging
** 4189-contact flip-chip LGA (up from 3647 contacts)
{{expand list}}

====New instructions ====
Cooper Lake introduced a number of {{x86|extensions|new instructions}}:

* [[BFLOAT16]] - A new data type for [[acceleration]] of [[neural processor|AI workloads]].
* {{x86|AVX512 BF16}} - AVX-512 [[Brain Float 16]] extension

== See also ==
* {{\\|Ice Lake (Server)}}
codename	Cooper Lake +
core count	28 +, 24 +, 20 +, 18 +, 16 + and 8 +
designer	Intel +
first launched	June 18, 2020 +
full page name	intel/microarchitectures/cooper lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Cooper Lake +
pipeline stages (max)	19 +
pipeline stages (min)	14 +