Editing intel/microarchitectures/tremont

{{intel title|Tremont|arch}}
{{microarchitecture
|atype=CPU
|name=Tremont
|designer=Intel
|manufacturer=Intel
|introduction=2019
|process=10 nm
|type=Superscalar
|oooe=Yes
|speculative=Yes
|renaming=Yes
|isa=x86-64
|extension=MOVBE
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AES
|extension 11=PCLMUL
|extension 12=RDRND
|extension 13=XSAVE
|extension 14=XSAVEOPT
|extension 15=FSGSBASE
|extension 16=PTWRITE
|extension 17=RDPID
|extension 18=SGX
|extension 19=UMIP
|extension 20=GFNI-SSE
|extension 21=CLWB
|extension 22=ENCLV
|extension 23=SHA
|core name=Elkhart Lake
|core name 2=Skyhawk Lake
|predecessor=Goldmont Plus
|predecessor link=intel/microarchitectures/goldmont plus
|successor=Gracemont
|successor link=intel/microarchitectures/gracemont
}}
'''Tremont''' is [[Intel]]'s successor to {{\\|Goldmont Plus}}, a [[10 nm]] microarchitecture for ultra-low power devices and microservers.

== Codenames ==
{| class="wikitable"
! Platform !! Core Name || PCH
|-
| || {{intel|Skyhawk Lake|l=core}} ||
|-
| Jacobsville || {{intel|Elkhart Lake|l=core}} || {{intel|Mule Creek Canyon|l=chipset}}
|-
| || {{intel|Jasper Lake|l=core}} ||
|}

== Brands ==
{{empty section}}

== Release Dates ==
Tremont was released in a number of products in late 2019.

== Technology ==
Tremont uses Intel's [[10 nm process]].

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[ICC]] || <code>-march=tremont</code> || <code>-mtune=tremont</code>
|-
| [[GCC]] || <code>-march=tremont</code> || <code>-mtune=tremont</code>
|-
| [[LLVM]] || <code>-march=tremont</code> || <code>-mtune=tremont</code>
|-
| [[Visual Studio]] || <code>/arch:?</code> || <code>/tune:?</code>
|}

=== CPUID ===
{| class="wikitable tc1 tc2 tc3 tc4"
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
|-
| rowspan="2" | ? || 0 || 0x6 || 0x8 || 0x6
|-
| colspan="4" | Family 6 Model 134
|}

== Architecture ==
Tremont is designed with significant single-thread performance in mind while focusing on low-power small silicon area cores.
=== Key changes from {{\\|Goldmont Plus}} ===
* Significant [[IPC]] uplift ([[Intel]] self-reported average 32% IPC accross proxy benchmarks such as [[SPEC CPU2006]]/[[SPEC CPU2017]])
* Front-end
** Redesigned front-end
*** New dual symmetric decode cluster
**** Out-of-order decode
**** 6-wide decode
***** 3-way decode per cluster
** Smarter [[prefetchers]]
** Improved [[branch predictor]]
*** Big-core level of performance
* Back-end
** larger ROB
** wide issue (10-wide)
* Execution Engine
** 2x store data ports (up from 1)


====New instructions ====
Tremont introduced a number of {{x86|extensions|new instructions}}:

* {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush
* {{x86|ENCLV|<code>ENCLV</code>}} - SGX oversubscription instructions
* {{x86|CLDEMOTE|<code>CLDEMOTE</code>}} - Cache line demote instruction
* {{x86|SSE_GFNI|<code>SSE_GFNI</code>}} - SSE-based Galois Field New Instructions
* Direct store instructions: MOVDIRI, MOVDIR64B 
* User wait instructions: TPAUSE, UMONITOR, UMWAIT
* Split Lock Detection - detection and cause an exception for split locks

=== Block Diagram ===
==== Individual Core ====
:[[File:tremont block diagram.svg|850px]]
codename	Tremont +
designer	Intel +
first launched	2019 +
full page name	intel/microarchitectures/tremont +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Tremont +
process	10 nm (0.01 μm, 1.0e-5 mm) +