Editing amd/microarchitectures/zen 2

{{amd title|Zen 2|arch}}
{{microarchitecture
|atype=CPU
|name=Zen 2
|designer=AMD
|manufacturer=GlobalFoundries
|manufacturer 2=TSMC
|introduction=2019
|process=14 nm
|process 2=7 nm
|process 3=12 nm
|type=Superscalar
|oooe=Yes
|speculative=Yes
|renaming=Yes
|stages=19
|decode=4-way
|isa=x86-64
|extension=MOVBE
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AVX
|extension 11=AVX2
|extension 12=AES
|extension 13=PCLMUL
|extension 14=RDRND
|extension 15=F16C
|extension 16=BMI
|extension 17=BMI2
|extension 18=RDSEED
|extension 19=ADCX
|extension 20=PREFETCHW
|extension 21=CLFLUSHOPT
|extension 22=XSAVE
|extension 23=SHA
|extension 24=CLZERO
|core name=Rome
|predecessor=Zen+
|predecessor link=amd/microarchitectures/zen+
|successor=Zen 3
|successor link=amd/microarchitectures/zen 3
}}
'''Zen 2''' is [[AMD]]'s successor to {{\\|Zen+}}, a [[7 nm process]] [[microarchitecture]] for mainstream mobile, desktops, workstations, and servers. Zen 2 will eventually be replaced by {{\\|Zen 3}}.

For performance desktop and mobile computing, Zen is branded as {{amd|Ryzen 3}}, {{amd|Ryzen 5}}, {{amd|Ryzen 7}} and {{amd|Ryzen Threadripper}} processors. For servers, Zen is branded as {{amd|EPYC}}.


{{work-in-progress}}


== History ==
[[File:amd zen 2 logo.png|right|thumb|Zen 2]]
Zen 2 is set to succeed {{\\|Zen}} in 2019. In February of 2017 Lisa Su, AMD's CEO announced their future roadmap to include Zen 2 and later {{\\|Zen 3}}. On Investor's Day May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 2 is set to utilize [[7 nm process]]. Initial details of Zen 2 and {{amd|Rome|l=core}} were unveiled during AMD's Next Horizon event on November 6 2018.

== Codenames ==
[[File:amd zen2-3 roadmap.png|thumb|right|Zen 2 on the roadmap]]
{{future information}}

{| class="wikitable"
|-
! Core !! C/T !! Target
|-
| {{amd|Rome|l=core}} || Up to 64/128 || High-end server [[multiprocessors]]
|-
| {{amd|Castle Peak|l=core}} || Up to 64/128? || workstation & enthusiasts market processors
|-
| {{amd|Matisse|l=core}} || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors
|-
| {{amd|Renoir|l=core}} || Up to 4/8? || Mainstream APUs with {{\\|Navi}} GPUs
|-
| {{amd|River Hawk|l=core}} || Up to 2/4 || Low-power/Cost-sensitive embedded processors with Navi GPU
|}

== Process technology ==
Zen 2 is fabricated on [[TSMC]]'s [[7 nm process]]. Some components of the chips (e.g., I/O die) are fabricated on [[GlobalFoundries]] [[12 nm process]].

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[GCC]] || <code>-march=znver2</code> || <code>-mtune=znver2</code>
|-
| [[LLVM]] || <code>-march=znver2</code> || <code>-mtune=znver2</code>
|}
* '''Note:''' Initial support in GCC 9 and LLVM 9.

== Architecture ==
Zen 2 inherits most of the design from {{\\|Zen+}} but improves the instruction stream bandwidth and floating-point throughput performance.


{{work-in-progress}}


=== Key changes from {{\\|Zen+}} ===
* [[7 nm process]] (from [[14 nm]])
** I/O die utilizes [[14 nm]]
* Core
** Higher [[IPC]] (AMD self-reported up to 15% IPC)
** Front-end
*** Improved [[branch prediction unit]]
**** Improved prefetcher
*** Improved µOP cache tags
*** Improved µOP cache
**** Larger µOP cache (4096 entries, up from 2048)
*** Increased dispatch bandwidth
** Back-end
*** Increased retire bandwidth (??-wide, up from 8-wide)
*** FPU
**** 2x wider datapath (256-bit, up from 128-bit)
**** 2x wider EUs (256-bit FMAs, up from 128-bit FMAs)
**** 2x wider LSU (2x256-bit L/S, up from 128-bit)
**** Improved mul latency (3 cycles, down from 4)
*** Integer
**** Increased number of registers (180, up from 168)
**** Additional AGU (3, up from 2)
**** Larger scheduler (4x16 ALU + 1x28 AGU, up from 4x14 ALU + 2x14 AGU
**** Larger Reorder Buffer (224, up from 192)
** Memory subsystem
*** 0.5x L1 instruction cache (32 KiB, down from 64 KiB)
*** 8-way associativity (from 4-way)
*** 1.33 larger L2 DTLB (2048-entry, up from 1536)
*** 48 entry store queue (was 44)
* {{amd|CCX}}
** 2x L3 cache slice (16 MiB, up from 8 MiB)
** Increased L3 latency (~40 cycles, up from ~35 cycles)
* Security
** In-silicon Spectre enhancements
** Increase number of keys/VMs supported
* I/O
** PCIe 4.0 (from 3.0)
** {{amd|Infinity Fabric}} 2
*** 2.3x transfer rate per link (25 GT/s, up from ~10.6 GT/s)
** Decoupling of MemClk from FClk, allowing 2:1 ratio in addition to 1:1
** DDR4-3200 support, up from DDR4-2933

{{expand list}}

==== New instructions ====
Zen 2 introduced a number of new [[x86]] instructions:

* <code>{{x86|CLWB}}</code> - Write back modified cache line and may retain line in cache hierarchy
* <code>{{x86|WBNOINVD}}</code> - Write back and do not flush internal caches, initiate same of external caches
* <code>{{x86|RDPID}}</code> - Read Processor ID

=== Block Diagram ===
==== Individual Core ====
{{empty section}}

=== Memory Hierarchy ===
{{empty section}}

== Core ==
Zen 2 largely builds on {{\\|Zen}}. Most of the fine details have not been revealed by AMD yet.


{{work-in-progress}}



=== Front End ===
In order to feed the backend, which has been widened to support 256-bit operation, the front-end throughput was improved. AMD reported that the [[branch prediction unit]] has been reworked. This includes improvements to the [[prefetcher]] and various undisclosed optimizations to the [[instruction cache]]. The [[µOP cache]] was also tweaked including changes to the µOP cache tags and the µOP cache itself which has been enlarged to improve the instruction stream throughput.

=== Execution Engine ===
AMD stated that both the dispatch bandwidth and the retire bandwidth has been increased.

==== Floating Point ====
The [[floating-point unit]] underwent major modifications in Zen 2. In {{\\|Zen}}, {{x86|AVX2}} 256 bit single and double precision vector floating-point data types were supported through the use of two 128 bit micro-ops per instruction. Likewise, the floating-point load and store operations were 128 bits wide. In Zen 2, the [[datapath]] and the [[execution units]] were widened to 256 bits, doubling the vector throughput of the core.

With two 256-bit [[fused multiply-add unit|FMAs]], Zen 2 is capable of 16 [[FLOPs]]/cycle.

== Rome ==
{{amd|Rome|l=core}} is codename for AMD's server chip based on the Zen 2 core. Like prior generation ({{amd|Naples|l=core}}), Rome utilizes a [[chiplet]] multi-chip package design. Each chip comprises of nine [[dies]] - one centralized I/O die and eight compute dies. The compute dies are fabricated on [[TSMC]]'s [[7 nm process]] in order to take advantage of the lower power and [[transistor density|higher density]]. On the other hand, the I/O makes use of [[GlobalFoundries]] mature [[14 nm process]].

The centralized I/O die incorporates eight {{amd|Infinity Fabric}} links, 128 [[PCIe]] Gen 4 lanes, and eight [[DDR4]] memory channels. The full capabilities of the I/O have not been disclosed yet. Attached to the I/O die are eight compute dies - each with eight Zen 2 core - for a total of 64 cores and 128 threads per chip.

== All Zen 2 chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->

{{comp table start}}
<table class="comptable sortable tc5 tc6 tc11 tc12">
{{comp table header|main|11:List of Zen 2 Processors}}
{{comp table header|cols|Family|Price|Launched|Cores|Threads|L3$|Base|Turbo|TDP|Mem Type}}
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 2]]
 |?full page name
 |?model number
 |?microprocessor family
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l3$ size#MiB
 |?base frequency#GHz
 |?turbo frequency#GHz
 |?tdp
 |?supported memory type
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 2]]}}
</table>
{{comp table end}}

== Bibliography ==
* AMD 'Tech Day', February 22, 2017
* AMD 2017 Financial Analyst Day, May 16, 2017
* AMD GCC 9 znver2 enablement [https://gcc.gnu.org/ml/gcc-patches/2018-10/msg01982.html patch]
* AMD 'Next Horizon', November 6, 2018
* AMD. Lisa Su ''Keynote''. May 26, 2019
* AMD 'Next Horizon Gaming' event at E3, June 10, 2019

== See Also ==
* Intel {{intel|Ice Lake|l=arch}}
codename	Zen 2 +
core count	4 +, 6 +, 8 +, 12 +, 16 +, 24 +, 32 + and 64 +
designer	AMD +
first launched	July 2019 +
full page name	amd/microarchitectures/zen 2 +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	TSMC + and GlobalFoundries +
microarchitecture type	CPU +
name	Zen 2 +
pipeline stages	19 +