Editing intel/cores/kaby lake u

{{intel title|Kaby Lake U|core}}
{{core
|name=Kaby Lake U
|image=kaby lake u (front; iris).png
|image size=250px
|caption=3-die config Iris Plus KBL-U (with OPC)
|image 2=kaby lake u (front; standard).png
|image 2 size=250px
|caption 2=2-die config KBL-U
|developer=Intel
|manufacturer=Intel
|first announced=August 30, 2016
|first launched=August 30, 2016
|isa=x86-64
|microarch=Kaby Lake
|word=64 bit
|proc=14 nm
|tech=CMOS
|clock min=1,800 MHz
|clock max=3,500 MHz
|package module 1={{packages/intel/fcbga-1356}}
|predecessor=Skylake U
|predecessor link=intel/cores/skylake u
|successor=Kaby Lake R
|successor link=intel/cores/kaby lake r
|successor 2=Coffee Lake U
|successor 2 link=intel/cores/coffee lake u
}}
'''Kaby Lake U''' ('''KBL-U''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a successor to {{intel|Skylake U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Kaby Lake U processors are fabricated on Intel's enhanced [[14 nm lithography process|14nm+ process]] and provide {{intel|kaby_lake#Key_changes_from_Skylake|slight enhancements over|l=arch}} comparable Skylake models.

== Overview ==
Kaby Lake U based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Note that some models (the Iris [[IGP]]s) are actually a 3 dice chip configuration since they incorporate an on-package cache (OPC) in addition to the hub and CPU. Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Kaby Lake U processors use {{intel|BGA-1356|Socket BGA-1356}} and all Iris models include 64 MiB of side cache.

{| class="wikitable"
! Standard !! Premium
|-
| 2-die configuration || 3-die configuration
|-
| GT2 Graphics || GT3 Graphics with OPC
|-
| [[File:kaby lake u (front; standard).png|250px]] || [[File:kaby lake u (front; iris).png|250px]]
|-
| [[File:kaby lake u (back; standard).png|250px]] || [[File:kaby lake u (back; iris).png|250px]]
|}
=== Common Features ===
[[File:kaby lake u (front; iris) angled.png|right|300px]]
All Kaby Lake U processors have the following:

* Dual-channel Memory
** Up to LPDDR3-1866, DDR3L-1600, DDR3L-2133, and DDR4-2133
** Up to 16-64 GiB
* 12x PCIe
* [[dual-core]] with 4 threads ({{intel|Celeron}} models only have 2 threads as they have {{intel|Hyper-Threading}} disabled)
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2)
** (Except for Pentium/Celeron which do not have AVX1/2)
* Support [[AHCI]], [[High Definition Audio]], 4-6x [[USB 3.0]] ports, 8-10x [[USB 2.0]] ports, 2-4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]]
* Graphics
** {{intel|HD Graphics 610}} (Gen 9.5 LP GT1), {{intel|HD Graphics 620}} ({{intel|Gen9.5|l=arch}} GT2), or {{intel|Iris Plus Graphics 640}}/{{intel|Iris Plus Graphics 650|650}} ({{intel|Gen9.5|l=arch}} GT3e)
** 3 independent displays supported
** Base frequency of 350 MHz
** Burst frequency of 1-1.15 GHz

{{clear}}

== Kaby Lake U Processors ==
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           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
<table class="comptable sortable tc16 tc17 tc18 tc19 tc20 tc21">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="21">List of Kaby Lake U Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="11">Main processor</th><th colspan="3">IGP</th><th colspan="6">Major Feature Diff</th></tr>
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th data-sort-type="number">C</th><th data-sort-type="number">T</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th></tr>
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake U]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core count
 |?thread count
 |?l3$ size
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 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |?has advanced vector extensions 2
 |?has intel trusted execution technology
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 |?has intel vpro technology
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=22:17
 |mainlabel=-
 |limit=100
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake U]]}}
</table>
{{comp table end}}

== See also ==
{{intel kaby lake core see also}}
* {{intel|Skylake|l=arch}}
** {{intel|Skylake U|l=core}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Kaby Lake U - Cores - Intel#package +
designer	Intel +
first announced	August 30, 2016 +
first launched	August 30, 2016 +
instance of	core +
isa	x86-64 +
main image	+ and +
main image caption	3-die config Iris Plus KBL-U (with OPC) + and 2-die config KBL-U +
manufacturer	Intel +
microarchitecture	Kaby Lake +
name	Kaby Lake U +
package	FCBGA-1356 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +