Editing arm holdings/microarchitectures/neoverse n1

{{armh title|Neoverse N1|arch}}
{{microarchitecture
|atype=CPU
|name=Ares
|designer=ARM Holdings
|manufacturer=TSMC
|introduction=February 20, 2019
|process=7 nm
|oooe=Yes
|speculative=Yes
|renaming=Yes
|predecessor=Cosmos
|predecessor link=arm_holdings/cosmos
|successor=Zeus
|successor link=arm_holdings/microarchitectures/zeus
}}
'''Neoverse N1''' (codename '''Ares''') is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.

== History ==
[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]]
Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares was officially unveiled on February 20, 2019.

== Release Dates ==
Ares was officially disclosed on February 20, 2019.

== Process Technology ==
Ares specifically takes advantage of the power and area advantages of the [[7 nm process]].

== Architecture ==
{{future information}}

* [[7 nm process]]
{{expand list}}

== Die ==
=== N1 core ===
* [[7 nm process]]
* 1 Core + L2
* 1.2 mm² die size (1C + 512 KiB L2)
* 1.4 mm² die size (1C + 1 MiB L2)
* 1 W @ 2.6 GHz (0.75 V), 1.8 W @ 3.1 W (1.0 V)


:[[File:neoverse n1 core die plot.png|600px]]

== Bibliography ==
* Drew Henry keynote, TechCon 2018 keynote.
* Drew Henry, direct communication
* Most of the technical details were obtained directly from Arm
codename	Neoverse N1 +
core count	4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 +
designer	ARM Holdings +
first launched	February 20, 2019 +
full page name	arm holdings/microarchitectures/neoverse n1 +
instance of	microarchitecture +
instruction set architecture	ARMv8.2 +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Neoverse N1 +
pipeline stages	11 +
process	7 nm (0.007 μm, 7.0e-6 mm) +