Editing bitmain/sophon/bm1880

{{bitmain title|Sophon BM1880}}
{{chip
|future=Yes
|name=Sophon BM1880
|no image=Yes
|designer=Bitmain
|manufacturer=TSMC
|model number=BM1880
|market=Edge Compute
|first announced=October 17, 2018
|first launched=October 17, 2018
|family=Sophon
|isa=RV32I
|isa family=RISC-V
|isa 2=ARMv8
|isa 2 family=ARM
|microarch=Cortex-A53
|microarch 2=RISC-V
|core name=Cortex-A53
|core name 2=RISC-V
|technology=CMOS
|max memory=4 GiB
|v core=0.9 V
|v io=1.8 V
|v io 2=3.3 V
|tdp typical=2.5 W
}}
'''Sophon BM1880''' is a [[neural processor]] designed by [[Bitmain]] launched in [[2018]] for edge applications. This chip is designed primarily for edge inference acceleration and has a peak performance of [[peak integer ops (8-bit)::2 TOPS]] (INT8) and a typical power consumption of 2.5 W.
core name	Cortex-A53 + and RISC-V +
core voltage	0.9 V (9 dV, 90 cV, 900 mV) +
designer	Bitmain +
family	Sophon +
first announced	October 17, 2018 +
first launched	October 17, 2018 +
full page name	bitmain/sophon/bm1880 +
has ecc memory support	false +
instance of	microprocessor +
io voltage	1.8 V (18 dV, 180 cV, 1,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	RV32I + and ARMv8 +
isa family	RISC-V + and ARM +
ldate	3000 +
manufacturer	TSMC +
market segment	Edge Compute +
max memory	4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	2 +
microarchitecture	Cortex-A53 + and RISC-V +
model number	BM1880 +
name	Sophon BM1880 +
peak integer ops (8-bit)	2,000,000,000,000 OPS (2,000,000,000 KOPS, 2,000,000 MOPS, 2,000 GOPS, 2 TOPS, 0.002 POPS, 2.0e-6 EOPS, 2.0e-9 ZOPS) +
supported memory type	DDR4-3200 +
tdp (typical)	2.5 W (2,500 mW, 0.00335 hp, 0.0025 kW) +
technology	CMOS +