Editing intel/microarchitectures/haswell (client)

{{intel title|Haswell|arch}}
{{microarchitecture
|atype=CPU
|name=Haswell
|designer=Intel
|manufacturer=Intel
|introduction=June 4, 2013
|phase-out=2015
|process=22 nm
|cores=2
|cores 2=4
|cores 3=6
|cores 4=8
|cores 5=16
|type=Superscalar
|speculative=Yes
|renaming=Yes
|stages min=14
|stages max=19
|isa=x86-64
|extension=MOVBE
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AVX
|extension 11=AVX2
|extension 12=AES
|extension 13=PCLMUL
|extension 14=FSGSBASE
|extension 15=RDRND
|extension 16=FMA3
|extension 17=BMI
|extension 18=BMI2
|extension 19=F16C
|extension 20=VT-x
|extension 21=VT-d
|extension 22=TXT
|extension 23=TSX
|l1i=32 KB
|l1i per=core
|l1i desc=8-way set associative
|l1d=32 KB
|l1d per=core
|l1d desc=8-way set associative
|l2=256 KB
|l2 per=core
|l2 desc=8-way set associative
|l3=1.5 MB
|l3 per=core
|l4=128 MB
|l4 per=package
|l4 desc=on Iris Pro GPUs only
|core name=Haswell H
|core name 2=Haswell E
|core name 3=Haswell EP
|core name 4=Haswell EX
|core name 5=Haswell DT
|core name 6=Haswell MB
|core name 7=Haswell ULT
|core name 8=Haswell ULX
|predecessor=Ivy Bridge
|predecessor link=intel/microarchitectures/ivy bridge
|successor=Broadwell
|successor link=intel/microarchitectures/broadwell
|pipeline=Yes
|OoOE=Yes
|issues=4
|inst=Yes
|cache=Yes
|core names=Yes
|succession=Yes
}}
'''Haswell''' ('''HSW''') is [[Intel]]'s  [[microarchitecture]] based on the [[22 nm process]] for mobile, desktops, and servers. Haswell, which was introduced in 2013, became the successor to {{\\|Ivy Bridge}}. Haswell is named after [[wikipedia:Haswell, Colorado|Haswell, Colorado]] (Originally Molalla after [[wikipedia:Molalla, Oregon|Molalla, Oregon]], it was later renamed due to the difficult pronunciation). In 2014 Intel introduced Haswell's successor, {{\\|Broadwell}}.

For desktop and mobile, Haswell is branded as 4th Generation Intel {{intel|Core}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v3}}, {{intel|Xeon E5|Xeon E5 v3}}, and {{intel|Xeon E7|Xeon E7 v3}}.
== Codenames ==
{| class="wikitable"
|-
! Core !! Abbrev !! Target
|-
| Haswell DT || HSW-DT || Desktops
|-
| Haswell MB || HSW-MB || Mobile/Laptops
|-
| Haswell H || HSW-H || All-in-ones
|-
| Haswell ULT || HSW-ULT || UltraBooks (MCPs)
|-
| Haswell ULX || HSW-ULX || Tablets/UltraBooks (SoCs)
|-
| Haswell EP || HSW-EP || Xeon chips
|-
| Haswell EX || HSW-EX || Xeon chips, QP
|-
| Haswell E || HSW-E || High-End Desktops (HEDT)
|}

== Process Technology ==
{{main|intel/microarchitectures/ivy bridge#Process_Technology|l1=Ivy Bridge § Process Technology}}
Haswell-based chips are manufactured on Intel's [[22 nm process]].

== Architecture ==
While sharing a lot of similarities with its predecessor {{\\|Ivy Bridge}}, Haswell introduces many new enhancements and features. Haswell is the first desktop-line of x86s by Intel tailored for a [[system on chip]] architecture. This is a significant move that will continue to be developed over the next couple of microarchitectures. Overall Haswell shares the same basic flow as {{\\|Sandy Bridge}} and {{\\|Ivy Bridge|Ivy}} but expends on them considerably in the execution engine with wider execution units and additional scheduler ports.

=== Key changes from {{\\|Ivy Bridge}} ===
[[File:haswell buff window.png|right|350px]]
* 3.5x performance/watt over {{\\|Nehalem}}
* Platform Controller Hub (PCH)
** Shrink from [[65 nm]] to [[32 nm]]
* Support for DDR4 (server/enthusiast segments)
* Full Integrated voltage regulator (FIVR)
* New C6 & C7 sleep states
* Cache
** L1D$ has double the bandwidth
*** Load: 64B/cycle (up from 32B/cycle)
*** Store: 32B/cycle (up from 16B/cycle)
** L2$ bandwidth to L1 is doubled
*** 64B/cycle (up from 32B/cycle)
** STLB been made to support 2MB pages
*** Table has been doubled to 1,024 entries 8-Way (up from 512, 4-way)
* Reorder Buffer (ROB) was increased to 192 entries (up from 168)
* Scheduler has been widened, (see [[#Front-end]])
** Increased to 60 entries (up from 54)
** Integer register file up 8 entries to 168
** FP register file up 24 entries to 168
** 2 additional execution ports (see [[#Execution_Units]])
* New memory model for {{x86|TSX|Transactional Synchronization Extensions}}

==== CPU changes ====
Haswell can execute more classes of instructions with 4 ops/cycle throughput. SandyBridge/Ivybridge could do so only for NOPs, CLC, some vector MOVs and some zeroing instructions (SUB, XOR and vector analogs).
* MOVSX and MOVZX have 4 op/cycle throughput for 8->32, 8->64 and 16->64 bit forms.
* Some ALU operations have 4 op/cycle throughput for 32-bit registers: XOR, OR, NEG, NOT, although not all (ADD, SUB, CMP and AND don't).
* Variable shifts and rotates (SHL r32, CL etc) latency increased from 1 cycle to 2 cycles, variable SHLD/SHRD from 2 cycles to 4 cycles.
* REP MOVS copy is twice as fast: now ~52 bytes/cycle.
* REP STOS fill is twice as fast: now ~30 bytes/cycle.

==== GPU changes ====
* Direct3D 11.1
* OpenGL 4.3
* OpenCL 1.2
* Four versions of GPU options codenamed GT1, GT2, GT3 and GT3 (with GT3e having a {{intel|Crystal Well|dedicated eDRAM L4$}})

====New instructions ====
Haswell introduced a number of new instructions:
* {{x86|AVX2|<code>AVX2</code>}} - Advanced Vector Extensions 2; an extension that extends most integer instructions to 256 bits vectors.
* {{x86|BMI1|<code>BMI1</code>}} - Bit Manipulation Instructions Sets 1
* {{x86|BMI2|<code>BMI2</code>}} - Bit Manipulation Instructions Sets 2
* {{x86|MOVBE|<code>MOVBE</code>}} - Move Big-Endian instruction
* {{x86|FMA3|<code>FMA3</code>}} - Floating Point Multiply Accumulate, 3 operands
* {{x86|TSX|<code>TSX</code>}} - Transactional Synchronization Extensions
* {{x86|INVPCID|<code>INVPCID</code>}} - Invalidate Process-Context Identifier
* {{x86|LZCNT|<code>LZCNT</code>}} - [[Leading zero count]]

=== Block Diagram ===

==== Individual Core ====
[[File:haswell block diagram.svg]]

=== Memory Hierarchy ===
The memory hierarchy in Haswell had a number of changes from its predecessor. The cache bandwidth for both load and store have been doubled (64B/cycle for load and 32B/cycle for store; up from 32/16 respectively). Significant enhancements have been done to support the new gather instructions and transactional memory. With Haswell new port 7 which adds an address generation for stores, up to two loads and one store are possible each cycle.

* Cache
** L1I Cache:
*** 32 KB 8-way [[set associative]]
**** 64 B line size
**** Write-back policy
**** shared by the two threads, per core
** L1D Cache:
*** 32 KB 8-way set associative
**** 64 B line size
**** shared by the two threads, per core
**** 4 cycles for fastest load-to-use
**** 64 Bytes/cycle load bandwidth
**** 32 Bytes/cycle store bandwidth
**** Write-back policy
** L2 Cache:
*** unified, 256 KB 8-way set associative
*** 11 cycles for fastest load-to-use
*** 64B/cycle bandwidth to L1$
*** Write-back policy
** L3 Cache:
*** 1.5 - 3 MB
*** Write-back policy
*** Per core
** L4 Cache:
*** 128 MB
*** Per package
*** Only on the {{intel|Iris Pro}} GPUs

Haswell TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB.

* TLBs:
** ITLB
*** 4KB page translations:
**** 128 entries; 4-way set associative
**** dynamic partition; divided between the two threads
*** 2MB/4MB page translations:
**** 8 entries; fully associative
**** Duplicated for each thread
** DTLB
*** 4KB page translations:
**** 64 entries; 4-way set associative
**** fixed partition; divided between the two threads
*** 2MB/4MB page translations:
**** 32 entries; 4-way set associative
*** 1G page translations:
**** 4 entries; 4-way set associative
** STLB
*** 4KB+2M page translations:
**** 1024 entries; 8-way set associative
**** shared

== Core ==
=== Pipeline ===
Haswell, like its predecessor Ivy Bridge, also has a dual-threaded and out-of-order pipeline. 

==== Front-end ====
The front-end is the complicated part of the microarchitecture as it deals with variable length x86 instructions ranging from 1 to 15 bytes. The main goal here is to fetch and decode correctly the next set of instructions. The caches have not changed in Haswell from {{\\|Ivy Bridge}}, with the [[L1i$]] still 32KB , 8-way set associative shared dynamically by the two threads. Instruction cache instruction fetching remains 16B/cycle. [[TLB]] is also still 128-entries, 4-way for 4KB pages and 8-entries, [[fully associative]] for 2MB page mode. The fetched instructions are then moved on to an instruction queue which has 40 entries, 20 for each thread. Haswell continued to improve the branch misses although the exact details have not been made public.

Haswell has the same µOps cache as Ivy Bridge - 1,536 entries organized in 32 sets of 8 cache lines with 6 µOps each. Hits can yield up to 4-µOps/cycle. The cache supports microcoded instructions (being pointers to ROM entries). Cache is shared by the two threads.

Following the [[instruction queue]], instructions are coded via the complex 4-way decoder. The decoder has 3 simple decoders and 1 complex decoder. In total, they are capable of emitting 3 single fused µOps and an additional 1-4 fused µOps. The unit handles both micro and macro fusions. [[Macro-fusion]] as a result of compatible adjacent µOps may be merged into a single µOp. Push and pops as well as call and return are also handled at this stage. 4 instructions, but with the aid of the macro-fusion, up to 5 instructions can be decoded each cycle.

==== Execution engine ====
Continuing with the decoder is the [[register renaming]] stage. This is crucial for out-of-order execution. In this stage the architectural x86 registers get mapped into one of the many physical registers. The integer physical register file (PRF) has been enlarged by 8 addition registers for a total 168. Likewise the FP PRF was extended by 24 registers bringing it too to 168 registers. The larger increase in the FP PRF is likely to accommodate the new {{x86|AVX2}} extension. The [[reorder buffer|ROB]] in Haswell has been increased to 192 entries (from 168 in Ivy) where each entry corresponds to a single µOp. The ROB is fixed split between the two threads. Additional scheduler resources get allocated as well - this includes stores, loads, and branch buffer entries. Note that due to how dependencies are handled, there may be more or less µOps than what was fed in. For the most part, the renamer is unified and deals with both integers and vectors. Resources, however, are partitioned between the two threads. Finally, as a last step, the µOps are matched with a port depending on their intended execution purpose. Up to 4 fused µOps may be renamed and handled per thread per cycle. Both the load and store in-flight units were increased to 72 and 42 entries respectively.

Haswell continues to use a unified scheduler for all µOps which holds 60 entries. µOps at this stage sit idle until they are cleared to be  executed via their assigned dispatch port. µOps may be held due to resource unavailability.

Following a successful execution, µOps retire at a rate of up to 4 fused µOps/cycle. Retirement is once again in-order and frees up any reserved resource (ROB entries, PRFs entries, and various other buffers).

===== Execution Units =====
Some of the biggest architectural changes were done in the area of the execution units. Haswell widened the scheduler by two ports - one new integer dispatch port and a new memory port bringing the total to 8 µOps/cycle. The various ports have also been rebalanced. The new port 6 adds another Integer ALU designs to improve integer workloads freeing up Port 0 and 1 for vector works. It also adds a second branch unit to low the congestion Port 0. The second port that was added, Port 7 adds a new [[address generation unit|AGU]]. This is largely due to the improvements for {{x86|AVX2}} that roughly doubled its throughput. Port 0 had its ALU/Mul/shifter extended to 256-bits; same is true for the vector ALU on port 1 and the ALU/shuffle on port 5. Additionally a 256-bit FMA unit were added to both port 0 and port 1. The change makes it possible for FMAs and FMULs to issue on both ports. In theory, Haswell can peak at over double the performance of {{\|Sandy Bridge}}, with 16 double / 32 single precision [[FLOP]]/cycle + Integer ALU option +  Vector operation.

The scheduler dispatches up to 8 ready µOps/cycle in [[FIFO]] order through the dispatch ports. µOps involving computational operations are sent to ports 0, 1, 5, and 6 to the appropriate unit. Likewise ports 2, 3, 4 and 7 are used for load/store and address calculations.

==Clock domains==
{{empty section}}
=== Overclocking ===
{{see also|intel/xmp|l1=Intel's XMP}}
{{oc warning}}

Overclocking needs to be done on an unlocked part such as the [[Core i7-5820K]], [[Core i7-5930K]], or [[Core i7-5960X]] Extreme Edition. Additionally those chips need to be paired with the Intel X99 Chipset.

[[File:haswell oc chips.png|500px|left]]

The 5930K and the 5820K are [[hexa-core]] parts whereas the [[5960X]] is an octa-core part. Between 28 and 40 [[PCIe]] lanes are possible with a core ratio of up to x80 the [[BCLK]].

[[File:haswell bclk.png|300px|right]]
Haswell provides a Coarsed BCLK ratios of either 100 MHz, 125 MHz, or 167 MHz (this was consequently changed in {{intel|Skylake#Overclocking|Skylake}}). The clock is generated internally by the chipset, but motherboard ODMs could generate it independently. A single BCLK from the PCH is fed in < 1 MHz steps, however in practice the input is very much limited by PCI Express and DMI PLL interface. This works out to 100 MHz ± 5-7% PEG/DMI @ 5:5, 125 MHz ±5-7% PEG/DMI @ 5:4, and 166.66 MHz ±5-7% @ 5:3.

<div style="display: table; padding: 5px;">
* '''f<sub>CORE</sub>''' = [[BCLK]] × [Core Ratio]
* '''f<sub>RING</sub>''' = BCLK × [Ring Ratio]
* '''F<sub>DDR</sub>''' = BCLK × [1.33/1.00] × [DDR Ratio]
</div>

All the clock domains in Haswell are derived from the BCLK (also called DMICLK). In the diagram on the right '''(xC)''' refers to the Core Frequency and is represented as a multiple of BCLK (Core Frequency = BCLK × Core Freq Multiplier up to x80). Likewise '''(xM)''' refers to the memory ratio (up to 2667 MT/s in granularity operations of 200 and 266 MHz) and Two additional multipliers to adjust the PEG(PCIe & Graphics)/DMI links which should remain at a nominal frequency of 100 MHz.

Voltage control is done by Haswell's new FIVER (Full Integrated Voltage Regulator) based architecture. This means that voltage arrives via the V<sub>CCin</sub> input from the motherboard into the processor and onto the voltage regulator (V<sub>CCin</sub> = [[SVID]] 1.8 V Nom up to 2.3 V+). Internally, the various voltage planes are all derived from there. This includes the V<sub>CORE</sub>, V<sub>RING</sub>, and V<sub>SA</sub>. With the memory voltage (V<sub>DDQ</sub> = 1.2 V Nom) provided from the motherboard with to its own rail.

{{clear}}

== Die ==
=== Client Die ===
Client die come in [[dual-core|2]], [[quad-core|4]], or [[octa-core|8]] cores setup with dual/quad being mainstream models and the [[octa-core]] being the high-end desktop.

====Dual-core ====
* 22 nm process
* 960,000,000 transistors
* 131 mm² die size, (I believe this is actually 181mm2, note the large graphics unit compared to quad-core)
* 2 CPU cores

: [[File:haswell die (dual-core).jpg|850px]]

====Quad-core ====
* [[22 nm process]]
* 1,400,000,000 transistors
* 177 mm² die size
* 4 CPU cores
* 1 GPU core
** 2x10xEU (80 ALUs)

: [[File:haswell die (quad-core).png|850px]]

: [[File:haswell die (quad-core) (annotated).png|850px]]

====Octa-core ====
* {{intel|Core i7-5960X}}
* [[Octa-core]] processor
* [[22 nm process]]
* 2,600,000,000 transistors
* 355.52 mm² die size
* 17.6 mm x 20.2 mm

:[[File:haswell (octa-core) die shot.png|650px]]


:[[File:haswell (octa-core) die shot (annotated).png|650px]]

=== Server Die ===

====Octadeca-core====
* [[18 cores]] processor
* [[22 nm process]]
* 5,690,000,000 transistors
* 622 mm² die size 

:[[File:intel xeon e7 v3.jpg|850px]]

== Added instructions ==
'''{{x86|AVX2}}''' - Integer data types were extended to 256-bit SIMD.

{{collist
| count = 4
| width = 650px
|
* {{x86|VBROADCASTI128}}
* {{x86|VBROADCASTSD}}
* {{x86|VBROADCASTSS}}
* {{x86|VEXTRACTI128}}
* {{x86|VGATHERDPD}}
* {{x86|VGATHERDPS}}
* {{x86|VGATHERQPD}}
* {{x86|VGATHERQPS}}
* {{x86|VINSERTI128}}
* {{x86|VMOVNTDQA}}
* {{x86|VMPSADBW}}
* {{x86|VPABSB}}
* {{x86|VPABSD}}
* {{x86|VPABSW}}
* {{x86|VPACKSSDW}}
* {{x86|VPACKSSWB}}
* {{x86|VPACKUSDW}}
* {{x86|VPACKUSWB}}
* {{x86|VPADDB}}
* {{x86|VPADDD}}
* {{x86|VPADDQ}}
* {{x86|VPADDSB}}
* {{x86|VPADDSW}}
* {{x86|VPADDUSB}}
* {{x86|VPADDUSW}}
* {{x86|VPADDW}}
* {{x86|VPALIGNR}}
* {{x86|VPAND}}
* {{x86|VPANDN}}
* {{x86|VPAVGB}}
* {{x86|VPAVGW}}
* {{x86|VPBLENDD}}
* {{x86|VPBLENDVB}}
* {{x86|VPBLENDW}}
* {{x86|VPBROADCASTB}}
* {{x86|VPBROADCASTD}}
* {{x86|VPBROADCASTQ}}
* {{x86|VPBROADCASTW}}
* {{x86|VPCMPEQB}}
* {{x86|VPCMPEQD}}
* {{x86|VPCMPEQQ}}
* {{x86|VPCMPEQW}}
* {{x86|VPCMPGTB}}
* {{x86|VPCMPGTD}}
* {{x86|VPCMPGTQ}}
* {{x86|VPCMPGTW}}
* {{x86|VPERM2I128}}
* {{x86|VPERMD}}
* {{x86|VPERMPD}}
* {{x86|VPERMPS}}
* {{x86|VPERMQ}}
* {{x86|VPGATHERDD}}
* {{x86|VPGATHERDQ}}
* {{x86|VPGATHERQD}}
* {{x86|VPGATHERQQ}}
* {{x86|VPHADDD}}
* {{x86|VPHADDSW}}
* {{x86|VPHADDW}}
* {{x86|VPHSUBD}}
* {{x86|VPHSUBSW}}
* {{x86|VPHSUBW}}
* {{x86|VPMADDUBSW}}
* {{x86|VPMADDWD}}
* {{x86|VPMASKMOVD}}
* {{x86|VPMASKMOVQ}}
* {{x86|VPMAXSB}}
* {{x86|VPMAXSD}}
* {{x86|VPMAXSW}}
* {{x86|VPMAXUB}}
* {{x86|VPMAXUD}}
* {{x86|VPMAXUW}}
* {{x86|VPMINSB}}
* {{x86|VPMINSD}}
* {{x86|VPMINSW}}
* {{x86|VPMINUB}}
* {{x86|VPMINUD}}
* {{x86|VPMINUW}}
* {{x86|VPMOVMSKB}}
* {{x86|VPMOVSXBD}}
* {{x86|VPMOVSXBQ}}
* {{x86|VPMOVSXBW}}
* {{x86|VPMOVSXDQ}}
* {{x86|VPMOVSXWD}}
* {{x86|VPMOVSXWQ}}
* {{x86|VPMOVZXBD}}
* {{x86|VPMOVZXBQ}}
* {{x86|VPMOVZXBW}}
* {{x86|VPMOVZXDQ}}
* {{x86|VPMOVZXWD}}
* {{x86|VPMOVZXWQ}}
* {{x86|VPMULDQ}}
* {{x86|VPMULHRSW}}
* {{x86|VPMULHUW}}
* {{x86|VPMULHW}}
* {{x86|VPMULLD}}
* {{x86|VPMULLW}}
* {{x86|VPMULUDQ}}
* {{x86|VPOR}}
* {{x86|VPSADBW}}
* {{x86|VPSHUFB}}
* {{x86|VPSHUFD}}
* {{x86|VPSHUFHW}}
* {{x86|VPSHUFLW}}
* {{x86|VPSIGNB}}
* {{x86|VPSIGND}}
* {{x86|VPSIGNW}}
* {{x86|VPSLLD}}
* {{x86|VPSLLDQ}}
* {{x86|VPSLLQ}}
* {{x86|VPSLLVD}}
* {{x86|VPSLLVQ}}
* {{x86|VPSLLW}}
* {{x86|VPSRAD}}
* {{x86|VPSRAVD}}
* {{x86|VPSRAW}}
* {{x86|VPSRLD}}
* {{x86|VPSRLDQ}}
* {{x86|VPSRLQ}}
* {{x86|VPSRLVD}}
* {{x86|VPSRLVQ}}
* {{x86|VPSRLW}}
* {{x86|VPSUBB}}
* {{x86|VPSUBD}}
* {{x86|VPSUBQ}}
* {{x86|VPSUBSB}}
* {{x86|VPSUBSW}}
* {{x86|VPSUBUSB}}
* {{x86|VPSUBUSW}}
* {{x86|VPSUBW}}
* {{x86|VPUNPCKHBW}}
* {{x86|VPUNPCKHDQ}}
* {{x86|VPUNPCKHQDQ}}
* {{x86|VPUNPCKHWD}}
* {{x86|VPUNPCKLBW}}
* {{x86|VPUNPCKLDQ}}
* {{x86|VPUNPCKLQDQ}}
* {{x86|VPUNPCKLWD}}
* {{x86|VPXOR}}
}}

'''{{x86|BMI1}}''' / '''{{x86|BMI2}}''' - Bit Manipulation Instructions Sets

{{collist
| count = 2
| width = 150px
|
* {{x86|ANDN}}
* {{x86|BEXTR}}
* {{x86|BLSI}}
* {{x86|BLSMSK}}
* {{x86|BLSR}}
* {{x86|BZHI}}
* {{x86|LZCNT}}
* {{x86|MULX}}
* {{x86|PDEP}}
* {{x86|PEXT}}
* {{x86|POPCNT}}
* {{x86|RORX}}
* {{x86|SARX}}
* {{x86|SHLX}}
* {{x86|SHRX}}
* {{x86|TZCNT}}
}}

'''{{x86|FMA3}}''' - Fused Multiply-Add instructions, 3 operands

{{collist
| count = 4
| width = 650px
|
* {{x86|VFMADD123PD}}
* {{x86|VFMADD123PS}}
* {{x86|VFMADD123SD}}
* {{x86|VFMADD123SS}}
* {{x86|VFMADD132PD}}
* {{x86|VFMADD132PS}}
* {{x86|VFMADD132SD}}
* {{x86|VFMADD132SS}}
* {{x86|VFMADD213PD}}
* {{x86|VFMADD213PS}}
* {{x86|VFMADD213SD}}
* {{x86|VFMADD213SS}}
* {{x86|VFMADD231PD}}
* {{x86|VFMADD231PS}}
* {{x86|VFMADD231SD}}
* {{x86|VFMADD231SS}}
* {{x86|VFMADD312PD}}
* {{x86|VFMADD312PS}}
* {{x86|VFMADD312SD}}
* {{x86|VFMADD312SS}}
* {{x86|VFMADD321PD}}
* {{x86|VFMADD321PS}}
* {{x86|VFMADD321SD}}
* {{x86|VFMADD321SS}}
* {{x86|VFMADDSUB123PD}}
* {{x86|VFMADDSUB123PS}}
* {{x86|VFMADDSUB132PD}}
* {{x86|VFMADDSUB132PS}}
* {{x86|VFMADDSUB213PD}}
* {{x86|VFMADDSUB213PS}}
* {{x86|VFMADDSUB231PD}}
* {{x86|VFMADDSUB231PS}}
* {{x86|VFMADDSUB312PD}}
* {{x86|VFMADDSUB312PS}}
* {{x86|VFMADDSUB321PD}}
* {{x86|VFMADDSUB321PS}}
* {{x86|VFMSUB123PD}}
* {{x86|VFMSUB123PS}}
* {{x86|VFMSUB123SD}}
* {{x86|VFMSUB123SS}}
* {{x86|VFMSUB132PD}}
* {{x86|VFMSUB132PS}}
* {{x86|VFMSUB132SD}}
* {{x86|VFMSUB132SS}}
* {{x86|VFMSUB213PD}}
* {{x86|VFMSUB213PS}}
* {{x86|VFMSUB213SD}}
* {{x86|VFMSUB213SS}}
* {{x86|VFMSUB231PD}}
* {{x86|VFMSUB231PS}}
* {{x86|VFMSUB231SD}}
* {{x86|VFMSUB231SS}}
* {{x86|VFMSUB312PD}}
* {{x86|VFMSUB312PS}}
* {{x86|VFMSUB312SD}}
* {{x86|VFMSUB312SS}}
* {{x86|VFMSUB321PD}}
* {{x86|VFMSUB321PS}}
* {{x86|VFMSUB321SD}}
* {{x86|VFMSUB321SS}}
* {{x86|VFMSUBADD123PD}}
* {{x86|VFMSUBADD123PS}}
* {{x86|VFMSUBADD132PD}}
* {{x86|VFMSUBADD132PS}}
* {{x86|VFMSUBADD213PD}}
* {{x86|VFMSUBADD213PS}}
* {{x86|VFMSUBADD231PD}}
* {{x86|VFMSUBADD231PS}}
* {{x86|VFMSUBADD312PD}}
* {{x86|VFMSUBADD312PS}}
* {{x86|VFMSUBADD321PD}}
* {{x86|VFMSUBADD321PS}}
* {{x86|VFNMADD123PD}}
* {{x86|VFNMADD123PS}}
* {{x86|VFNMADD123SD}}
* {{x86|VFNMADD123SS}}
* {{x86|VFNMADD132PD}}
* {{x86|VFNMADD132PS}}
* {{x86|VFNMADD132SD}}
* {{x86|VFNMADD132SS}}
* {{x86|VFNMADD213PD}}
* {{x86|VFNMADD213PS}}
* {{x86|VFNMADD213SD}}
* {{x86|VFNMADD213SS}}
* {{x86|VFNMADD231PD}}
* {{x86|VFNMADD231PS}}
* {{x86|VFNMADD231SD}}
* {{x86|VFNMADD231SS}}
* {{x86|VFNMADD312PD}}
* {{x86|VFNMADD312PS}}
* {{x86|VFNMADD312SD}}
* {{x86|VFNMADD312SS}}
* {{x86|VFNMADD321PD}}
* {{x86|VFNMADD321PS}}
* {{x86|VFNMADD321SD}}
* {{x86|VFNMADD321SS}}
* {{x86|VFNMSUB123PD}}
* {{x86|VFNMSUB123PS}}
* {{x86|VFNMSUB123SD}}
* {{x86|VFNMSUB123SS}}
* {{x86|VFNMSUB132PD}}
* {{x86|VFNMSUB132PS}}
* {{x86|VFNMSUB132SD}}
* {{x86|VFNMSUB132SS}}
* {{x86|VFNMSUB213PD}}
* {{x86|VFNMSUB213PS}}
* {{x86|VFNMSUB213SD}}
* {{x86|VFNMSUB213SS}}
* {{x86|VFNMSUB231PD}}
* {{x86|VFNMSUB231PS}}
* {{x86|VFNMSUB231SD}}
* {{x86|VFNMSUB231SS}}
* {{x86|VFNMSUB312PD}}
* {{x86|VFNMSUB312PS}}
* {{x86|VFNMSUB312SD}}
* {{x86|VFNMSUB312SS}}
* {{x86|VFNMSUB321PD}}
* {{x86|VFNMSUB321PS}}
* {{x86|VFNMSUB321SD}}
* {{x86|VFNMSUB321SS}}
}}

'''{{x86|MOVBE}}''' - Move Big-Endian instruction

{{collist
| count = 1
| width = 650px
|
* {{x86|MOVBE}}
}}

'''{{x86|TSX}}''' - Transactional Synchronization Extensions

{{collist
| count = 1
| width = 150px
|
* {{x86|XABORT}}
* {{x86|XBEGIN}}
* {{x86|XEND}}
* {{x86|XTEST}}
}}

== Cores ==
{{empty section}}

== All Haswell Chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc6 tc7 tc20 tc21 tc22 tc23 tc24 tc25">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="19">List of Haswell Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="5">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">IGP</th></tr>
{{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Frequency, Turbo}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Haswell]] [[max cpu count::1]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?turbo frequency (2 cores)#GHz
 |?turbo frequency (3 cores)#GHz
 |?turbo frequency (4 cores)#GHz
 |?max memory#GiB
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=20
 |mainlabel=-
 |limit=200
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Haswell]]}}
</table>
{{comp table end}}

== References ==
* Hammarlund, Per, et al. "Haswell: The fourth-generation intel core processor." IEEE Micro 34.2 (2014): 6-20.
* Dan Ragland, Overclocking System Architect, 2015 IDF, in San Francisco, Session RPCS001 ("Overclocking 6th Generation Intel® Core™ Processors!"), August 18, 2015

== Documents ==
* [[:File:haswell isa extension.pdf|Haswell new ISA extensions]]
codename	Haswell +
core count	2 +, 4 +, 6 +, 8 +, 16 +, 10 +, 12 +, 14 + and 18 +
designer	Intel +
first launched	June 4, 2013 +
full page name	intel/microarchitectures/haswell (client) +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Haswell +
phase-out	2015 +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	22 nm (0.022 μm, 2.2e-5 mm) +