Editing amd/cores/castle peak

{{amd title|Castle Peak|core}}
{{core
|name=Castle Peak
|no image=Yes
|developer=AMD
|first announced=2019
|first launched=2019
|isa=x86-64
|microarch=Zen + or Zen 2
|word=64 bit
|proc=12 nm or 7 nm
|tech=CMOS
|package name 1=amd,socket_tr4
|predecessor=Colfax
|predecessor link=amd/cores/colfax
}}
'''Castle Peak''' is codename for highest-performance enthusiasts [[microprocessors]] from AMD, due to be releasd in 2019. Castle Peak will be based on either the {{amd|Zen 2|l=arch}} microarchitecture and [[7 nm process]], or the {{amd|Zen+|l=arch}} microarchitecture and [[12 nm process]]. This family serves as a successor to {{\\|Colfax}}.


{{future information}}


== Overview ==
{{empty section}}

=== Common Features ===
{{empty section}}

== Castle Peak Processors ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc5 tc6">
{{comp table header|main|10:List of Castle Peak Processors}}
{{comp table header|cols|Family|Price|Launched|Cores|Threads|TDP|L2$|L3$|Base|Turbo}}
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
 |?full page name
 |?model number
 |?microprocessor family
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Castle Peak]]}}
</table>
{{comp table end}}
chipset	TRX40 + and WRX80 +
designer	AMD +
first announced	November 7, 2019 +
first launched	November 25, 2019 +
instance of	core +
isa	x86-64 +
isa family	x86 +
manufacturer	TSMC + and GlobalFoundries +
microarchitecture	Zen 2 +
name	Castle Peak +
package	sTRX4 +, sWRX8 + and FCLGA-4094 +
process	7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +
socket	sTRX4 + and sWRX8 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +