Editing hisilicon/kunpeng/920-6426

{{hisilicon title|Hi1620}}
{{chip
|future=Yes
|name=Hi1620
|no image=Yes
|designer=HiSilicon
|designer 2=ARM Holdings
|manufacturer=TSMC
|model number=Hi1620
|market=Server
|first announced=September, 2018
|first launched=September, 2018
|family=Hi16xx
|frequency=3,000 MHz
|isa=ARMv8
|isa family=ARM
|microarch=Cortex-A73
|core name=Cortex-A73
|technology=CMOS
|word size=64 bit
|core count=48
|thread count=48
|max cpus=2
|max memory=512 GiB
}}
'''Hi1620''' is a planned [[octatetraconta-core]] {{arch|64}} [[ARM]] server microprocessor set to be introduced by HiSilicon in late-2018. Fabricated by [[TSMC]] on a [[? nm process]], this chip incorporates 48 {{armh|Cortex-A73}} cores operating at 3 GHz. The Hi1620 supports up to 512 GiB of quad-channel DDR4-2400 memory.


{{unknown features}}

== Cache ==
{{main|arm holdings/microarchitectures/cortex-a72#Memory_Hierarchy|l1=Cortex-A72 § Cache}}
{{cache size
|l1 cache=3.75 MiB
|l1i cache=2.25 MiB
|l1i break=48x48 KiB
|l1i desc=8-way set associative
|l1d cache=1.5 MiB
|l1d break=48x32 KiB
|l1d desc=8-way set associative
|l2 cache=12 MiB
|l2 break=48x256 KiB
|l2 desc=8-way set associative
|l3 cache=48 MiB
|l3 break=48x1 MiB
|l3 desc=16-way set associative
}}

== Memory controller ==
{{memory controller
|type=DDR4-2400
|ecc=Yes
|max mem=512 GiB
|controllers=1
|channels=4
|width=64 bit
|max bandwidth=71.53 GiB/s
|bandwidth schan=17.88 GiB/s
|bandwidth dchan=35.76 GiB/s
|bandwidth qchan=71.53 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=16
|pcie config=2x8
}}
}}
== Features ==
{{arm features
|thumb=No
|thumb2=No
|thumbee=No
|vfpv1=No
|vfpv2=No
|vfpv3=No
|vfpv3-d16=No
|vfpv3-f16=No
|vfpv4=No
|vfpv4-d16=No
|vfpv5=No
|neon=Yes
|trustzone=No
|jazelle=No
|wmmx=No
|wmmx2=No
|pmuv3=No
|crc32=Yes
|crypto=No
|fp=No
|fp16=No
|profile=No
|ras=No
|simd=No
|rdm=No
}}

== Utilizing devices ==
* [[used by::HiSilicon D06]]

{{expand list}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Kunpeng 920-6426 - HiSilicon#pcie +
base frequency	2,600 MHz (2.6 GHz, 2,600,000 kHz) +
core count	64 +
core name	TaiShan v110 +
designer	HiSilicon + and ARM Holdings +
die count	3 +
family	Hi16xx +
first announced	September 2018 +
first launched	January 7, 2019 +
full page name	hisilicon/kunpeng/920-6426 +
has ecc memory support	true +
instance of	microprocessor +
is multi-chip package	true +
isa	ARMv8.2 +
isa family	ARM +
l1$ size	8,192 KiB (8,388,608 B, 8 MiB) +
l1d$ size	4,096 KiB (4,194,304 B, 4 MiB) +
l1i$ size	4,096 KiB (4,194,304 B, 4 MiB) +
l2$ size	32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
l3$ size	64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldate	January 7, 2019 +
main image	+
manufacturer	TSMC +
market segment	Server +
max cpu count	4 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels	8 +
max sata ports	2 +
max usb ports	4 +
microarchitecture	TaiShan v110 +
model number	920-6426 +
name	Kunpeng 920-6426 +
series	920 +
smp max ways	4 +
supported memory type	DDR4-2933 +
tdp	195 W (195,000 mW, 0.261 hp, 0.195 kW) +
technology	CMOS +
thread count	64 +
transistor count	20,000,000,000 +
used by	HiSilicon D06 +, TaiShan 5280 +, TaiShan 5290 +, TaiShan X6000 + and TaiShan 2280 +
word size	64 bit (8 octets, 16 nibbles) +