Editing intel/xeon silver/4114t

{{intel title|Xeon Silver 4114T}}
{{chip
|name=Xeon Silver 4114T
|image=skylake sp (basic).png
|designer=Intel
|manufacturer=Intel
|model number=4114T
|market=Server
|first announced=July 11, 2017
|first launched=July 11, 2017
|family=Xeon Silver
|series=4000
|locked=Yes
|frequency=2,200 MHz
|turbo frequency1=3,000 MHz
|clock multiplier=22
|isa=x86-64
|isa family=x86
|microarch=Skylake (server)
|platform=Purley
|chipset=Lewisburg
|core name=Skylake SP
|core family=6
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=10
|thread count=20
|max cpus=2
|max memory=768 GiB
|tdp=85 W
|tcase min=0 °C
|tcase max=77 °C
|package module 1={{packages/intel/fclga-3647}}
}}
'''Xeon Silver 4114T''' is a {{arch|64}} [[deca-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4114T, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.2 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.

This specific model (''T'') has 10 years extended life guarantees designed to be [[NEBS]]-friendly for use in [[NEBS]]-complaint applications.
== Cache ==
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
{{cache size
|l1 cache=640 KiB
|l1i cache=320 KiB
|l1i break=10x32 KiB
|l1i desc=8-way set associative
|l1d cache=320 KiB
|l1d break=10x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=10 MiB
|l2 break=10x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=13.75 MiB
|l3 break=10x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2400
|ecc=Yes
|max mem=768 GiB
|controllers=2
|channels=6
|max bandwidth=107.3 GiB/s
|bandwidth schan=17.88 GiB/s
|bandwidth dchan=35.76 GiB/s
|bandwidth qchan=71.53 GiB/s
|bandwidth hchan=107.3 GiB/s
}}

== Expansions ==
{{expansions
| pcie revision      = 3.0
| pcie lanes         = 48
| pcie config        = x16
| pcie config 2      = x8
| pcie config 3      = x4
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes
|avx512f=Yes
|avx512cd=Yes
|avx512er=No
|avx512pf=No
|avx512bw=Yes
|avx512dq=Yes
|avx512vl=Yes
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx5124vnniw=No
|avx512vpopcntdq=No
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|tbt1=No
|tbt2=Yes
|tbmt3=No
|bpt=No
|eist=Yes
|sst=Yes
|flex=No
|fastmem=No
|ivmd=Yes
|intelnode=Yes
|kpt=Yes
|ptt=Yes
|mbe=Yes
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=Yes
|txt=Yes
|ht=Yes
|vpro=Yes
|vtx=Yes
|vtd=No
|ept=Yes
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
}}

== Frequencies ==
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
{{frequency table
|freq_base=2,200 MHz
|freq_1=3,000 MHz
|freq_2=3,000 MHz
|freq_3=2,800 MHz
|freq_4=2,800 MHz
|freq_5=2,700 MHz
|freq_6=2,700 MHz
|freq_7=2,700 MHz
|freq_8=2,700 MHz
|freq_9=2,500 MHz
|freq_10=2,500 MHz
|freq_avx2_base=1,800 MHz
|freq_avx2_1=2,900 MHz
|freq_avx2_2=2,900 MHz
|freq_avx2_3=2,700 MHz
|freq_avx2_4=2,700 MHz
|freq_avx2_5=2,300 MHz
|freq_avx2_6=2,300 MHz
|freq_avx2_7=2,300 MHz
|freq_avx2_8=2,300 MHz
|freq_avx2_9=2,200 MHz
|freq_avx2_10=2,200 MHz
|freq_avx512_base=1,100 MHz
|freq_avx512_1=1,800 MHz
|freq_avx512_2=1,800 MHz
|freq_avx512_3=1,600 MHz
|freq_avx512_4=1,600 MHz
|freq_avx512_5=1,500 MHz
|freq_avx512_6=1,500 MHz
|freq_avx512_7=1,500 MHz
|freq_avx512_8=1,500 MHz
|freq_avx512_9=1,400 MHz
|freq_avx512_10=1,400 MHz
}}

[[Category:microprocessor models by intel based on skylake low core count die]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Silver 4114T - Intel#io +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
chipset	Lewisburg +
clock multiplier	22 +
core count	10 +
core family	6 +
core name	Skylake SP +
core stepping	U0 +
designer	Intel +
family	Xeon Silver +
first announced	July 11, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon silver/4114t +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	640 KiB (655,360 B, 0.625 MiB) +
l1d$ description	8-way set associative +
l1d$ size	320 KiB (327,680 B, 0.313 MiB) +
l1i$ description	8-way set associative +
l1i$ size	320 KiB (327,680 B, 0.313 MiB) +
l2$ description	16-way set associative +
l2$ size	10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l3$ description	11-way set associative +
l3$ size	13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) +
ldate	July 11, 2017 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	350.15 K (77 °C, 170.6 °F, 630.27 °R) +
max cpu count	2 +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	4114T +
name	Xeon Silver 4114T +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
s-spec	SR3MM +
s-spec (qs)	QN7A +
series	4000 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	9.6 GT/s +
smp max ways	2 +
socket	LGA-3647 + and Socket P +
supported memory type	DDR4-2400 +
tdp	85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technology	CMOS +
thread count	20 +
turbo frequency (1 core)	3,000 MHz (3 GHz, 3,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +