Editing intel/xeon e5/e5-2696 v4

{{intel title|Xeon E5-2696 v4}}
{{mpu
| name                = Xeon E5-2696 v4
| no image            = Yes
| image               = 
| image size          = 
| caption             = 
| designer            = Intel
| manufacturer        = Intel
| model number        = E5-2696 v4
| part number         = CM8066002402501
| part number 2       = 
| part number 3       = 
| part number 4       = 
| market              = Server
| first announced     = June 20, 2016
| first launched      = June 20, 2016
| last order          = 
| last shipment       = 
| release price       = 

| family              = Xeon E5
| series              = E5-2000
| locked              = Yes
| frequency           = 2,200 MHz
| turbo frequency     = Yes
| turbo frequency1    = 3,700 MHz
| turbo frequency2    = 3,700 MHz
| turbo frequency3    = 3,500 MHz
| turbo frequency4    = 3,400 MHz
| turbo frequency5    = 3,300 MHz
| turbo frequency6    = 3,200 MHz
| turbo frequency7    = 3,100 MHz
| turbo frequency8    = 3,000 MHz
| turbo frequency9    = 2,900 MHz
| turbo frequency10   = 2,800 MHz
| turbo frequency11   = 2,800 MHz
| turbo frequency12   = 2,800 MHz
| turbo frequency13   = 2,800 MHz
| turbo frequency14   = 2,800 MHz
| turbo frequency15   = 2,800 MHz
| turbo frequency16   = 2,800 MHz
| turbo frequency17   = 2,800 MHz
| turbo frequency18   = 2,800 MHz
| turbo frequency19   = 2,800 MHz
| turbo frequency20   = 2,800 MHz
| turbo frequency21   = 2,800 MHz
| turbo frequency22   = 2,800 MHz
| bus type            = QPI
| bus speed           = 4,800 MHz
| bus rate            = 9.6 GT/s
| bus links           = 2
| clock multiplier    = 22
| s-spec              = SR2J0
| s-spec es           = 
| s-spec qs           = 
| cpuid               = 406F1

| microarch           = Broadwell
| platform            = Grantley EP 2S
| chipset             = C610 Series
| core name           = Broadwell EP
| core family         = 6
| core model          = 4F
| core stepping       = B0
| process             = 14 nm
| transistors         = 7,200,000,000
| technology          = CMOS
| die size            = 456.12 mm²
| word size           = 64 bit
| core count          = 22
| thread count        = 44
| max cpus            = 2
| max memory          = 1,536 GiB


| v core              = 1.82 V
| v core tolerance    = 
| v io                = 1.2 V
| v io tolerance      = 3%
| sdp                 = 
| tdp                 = 150 W
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| tjunc min           = 
| tjunc max           = 
| tcase min           = 0 °C
| tcase max           = ? °C
| tstorage min        = -25 °C
| tstorage max        = 125 °C

| packaging           = Yes
| package 0           = FCLGA-2011-v3
| package 0 type      = FCLGA
| package 0 pins      = 2011
| package 0 pitch     = 0.8814 mm
| package 0 width     = 52.5 mm
| package 0 length    = 45.0 mm
| package 0 height    = 5.316 mm
| socket 0            = LGA-2011-v3
| socket 0 type       = LGA
}}
The '''Xeon E5-2696 v4''' is a {{arch|64}} [[docosa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for 2S environments. Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.7 GHz for a single active core, this MPU has a TDP of 150 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).

== Cache ==
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
{{cache info
|l1i cache=704 KiB
|l1i break=22x32 KiB
|l1i desc=8-way set associative
|l1i extra=(per core, write-back)
|l1d cache=704 KiB
|l1d break=22x32 KiB
|l1d desc=8-way set associative
|l1d extra=(per core, write-back)
|l2 cache=5.5 MiB
|l2 break=22x256 KiB
|l2 desc=8-way set associative
|l2 extra=(per core, write-back)
|l3 cache=55 MiB
|l3 break=22x2.5 MiB
|l3 desc=20-way set associative
|l3 extra=(shared, per core, write-back)
}}

== Graphics ==
This microprocessor has no [[integrated graphics processing unit]].

== Memory controller ==
{{integrated memory controller
| type               = DDR4-2400
| controllers        = 1
| channels           = 4
| ecc support        = Yes
| max bandwidth      = 71.53 GiB/s
| bandwidth schan    = 17.88 GiB/s
| bandwidth dchan    = 35.76 GiB/s
| max memory         = 1,536 GiB
| pae                = 46 bit
}}

== Expansions ==
{{expansions
| pcie revision      = 3.0
| pcie lanes         = 40
| pcie config        = x4
| pcie config 1      = x8
| pcie config 2      = x16
}}

== Features == 
{{x86 features
| em64t       = Yes
| nx          = Yes
| txt         = Yes
| tsx         = Yes
| vpro        = Yes
| ht          = Yes
| tbt1        = 
| tbt2        = Yes
| tbmt3       = 
| bpt         = 
| vt-x        = Yes
| vt-d        = Yes
| ept         = Yes
| mmx         = Yes
| sse         = Yes
| sse2        = Yes
| sse3        = Yes
| ssse3       = Yes
| sse4.1      = Yes
| sse4.2      = Yes
| aes         = Yes
| pclmul      = Yes
| avx         = Yes
| avx2        = Yes
| bmi         = Yes
| bmi1        = Yes
| bmi2        = Yes
| f16c        = Yes
| fma3        = Yes
| mpx         = 
| sgx         = 
| eist        = Yes
| secure key  = Yes
| os guard    = Yes
| intel at    = 
| intel ipt   = 
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon E5-2696 v4 - Intel#io +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links	2 +
bus rate	9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) +
bus speed	4,800 MHz (4.8 GHz, 4,800,000 kHz) +
bus type	QPI +
chipset	C610 Series +
clock multiplier	22 +
core count	22 +
core family	6 +
core model	4F +
core name	Broadwell EP +
core stepping	B0 +
core voltage	1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid	406F1 +
designer	Intel +
die area	456.12 mm² (0.707 in², 4.561 cm², 456,120,000 µm²) +
family	Xeon E5 +
first announced	June 20, 2016 +
first launched	June 20, 2016 +
full page name	intel/xeon e5/e5-2696 v4 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel vPro Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel enhanced speedstep technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
io voltage	1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance	3% +
l1d$ description	8-way set associative +
l1d$ size	704 KiB (720,896 B, 0.688 MiB) +
l1i$ description	8-way set associative +
l1i$ size	704 KiB (720,896 B, 0.688 MiB) +
l2$ description	8-way set associative +
l2$ size	5.5 MiB (5,632 KiB, 5,767,168 B, 0.00537 GiB) +
l3$ description	20-way set associative +
l3$ size	55 MiB (56,320 KiB, 57,671,680 B, 0.0537 GiB) +
ldate	June 20, 2016 +
manufacturer	Intel +
market segment	Server +
max cpu count	2 +
max memory	1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes	40 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Broadwell +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	E5-2696 v4 +
name	Xeon E5-2696 v4 +
part number	CM8066002402501 +
platform	Grantley EP 2S +
process	14 nm (0.014 μm, 1.4e-5 mm) +
s-spec	SR2J0 +
series	E5-2000 +
smp max ways	2 +
tdp	150 W (150,000 mW, 0.201 hp, 0.15 kW) +
technology	CMOS +
thread count	44 +
transistor count	7,200,000,000 +
turbo frequency (10 cores)	2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (11 cores)	2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (12 cores)	2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (13 cores)	2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (14 cores)	2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (15 cores)	2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (16 cores)	2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (17 cores)	2,800 MHz +
turbo frequency (18 cores)	2,800 MHz +
turbo frequency (19 cores)	2,800 MHz +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
turbo frequency (20 cores)	2,800 MHz +
turbo frequency (21 cores)	2,800 MHz +
turbo frequency (22 cores)	2,800 MHz +
turbo frequency (2 cores)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
turbo frequency (3 cores)	3,500 MHz (3.5 GHz, 3,500,000 kHz) +
turbo frequency (4 cores)	3,400 MHz (3.4 GHz, 3,400,000 kHz) +
turbo frequency (5 cores)	3,300 MHz (3.3 GHz, 3,300,000 kHz) +
turbo frequency (6 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (7 cores)	3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (8 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (9 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +