Editing intel/microarchitectures/goldmont plus

{{intel title|Goldmont Plus|arch}}
{{microarchitecture
|atype=CPU
|name=Goldmont Plus
|designer=Intel
|manufacturer=Intel
|introduction=November 7, 2017
|process=14 nm
|cores=2
|cores 2=4
|type=Superscalar
|oooe=Yes
|speculative=Yes
|renaming=Yes
|isa=x86-16
|isa 2=x86-32
|isa 3=x86-64
|extension=MOVBE
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AES
|extension 11=PCLMUL
|extension 12=RDRND
|extension 13=SHA
|l1i=32 KiB
|l1i per=Core
|l1i desc=8-way set associative
|l1d=24 KiB
|l1d per=Core
|l1d desc=6-way set associative
|l2=2 MiB
|l2 per=2 Cores
|l2 desc=16-way set associative
|core name=Gemini Lake
|predecessor=Goldmont
|predecessor link=intel/microarchitectures/goldmont
}}
'''Goldmont Plus''' ('''GLM+''') is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices serving as a successor to {{\\|Goldmont}}. Goldmont Plus-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium (2009)|Pentium}}, and {{intel|Celeron}} families.

== Codenames ==
{| class="wikitable"
|-
! Platform !! Core !! Target
|-
| {{intel|Gemini Lake}} || {{intel|Gemini Lake|l=core}} || Entry-level PCs, Communications, Storage, Tablets
|}

== Architecture ==
{{future information}}
=== Key changes from {{\\|Goldmont}} ===
* 4-way decode (from 3-way)<ref>https://patchwork.kernel.org/patch/9836747/</ref>
* VP9 10-bit Profile2 hardware decoding
* Integrated native HDMI 2.0 controller
* Integrated Intel Wireless-AC(Wi-Fi/BT CNVi)
* 4 MiB L2 cache per duplex (Up from 2 MiB)

* Graphics
** {{intel|Gen 9.5|l=arch}} GPUs 
** HD Graphics 50x '''→''' UHD Graphics 60x
*** {{intel|HD Graphics 505}} '''→''' {{intel|UHD Graphics 605}} (Pentium Silver J/N 5xxx with 18EU)
*** {{intel|HD Graphics 500}} '''→''' {{intel|UHD Graphics 600}} (Celeron J/N 4xxx with 12EU)

====New instructions ====
Goldmont Plus introduced a number of {{x86|extensions|new instructions}}:

* {{x86|SGX1|<code>SGX1</code>}} - Software Guard Extensions, Version 1
* UMIP
* PTWRITE
* RDPID

=== Block Diagram ===
{{empty section}}
=== Memory Hierarchy ===
* Cache
** Hardware prefetchers
** L1 Cache:
*** 32 [[KiB]] 8-way [[set associative]] instruction, 64 B line size
*** 24 KiB 6-way set associative data, 64 B line size
*** Per core
** L2 Cache:
*** 4 MiB 16-way set associative, 64 B line size
*** Per 2 cores
** L3 Cache:
*** No level 3 cache
** RAM
*** Maximum of 1 [[GiB]], 2 GiB, 4 GiB, 8 GiB
*** dual 32-bit channels, 1 or 2 ranks per channel

=== Multithreading ===
Goldmont Plus, like {{\\|Goldmont}} has no support for Intel Hyper-Threading Technology.

== Core ==
{{empty section}}
codename	Goldmont Plus +
core count	2 + and 4 +
designer	Intel +
first launched	December 11, 2017 +
full page name	intel/microarchitectures/goldmont plus +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Goldmont Plus +
process	14 nm (0.014 μm, 1.4e-5 mm) +