Editing nxp/qoriq

{{nxp title|QorIQ}}
{{ic family
| title             = QorIQ
| image             = 
| caption           = 
| no image          = Yes
| developer         = Freescale
| developer 2       = NXP
| manufacturer      = IBM
| manufacturer 2    = TSMC
| type              = System on Chips
| first announced   = June 16, 2008
| first launched    = June 16, 2008
| arch              = POWER & ARM Communication SoC
| isa               = 
| microarch         = 
| microarch 2       = 
| microarch 3       = 
| word              = 32 bit
| word 2            = 64 bit
| proc              = 45 nm
| proc 2            = 32 nm
| proc 3            = 20 nm
| proc 4            = 16 nm
| tech              = CMOS
| clock min         = 533 MHz
| clock max         = 2,000 MHz
| package           = 
| package 2         = 
| package 3         = 
| package 4         = 
| socket            = 
| socket 2          = 

| succession       = Yes
| predecessor      = PowerQUICC
| predecessor link = freescale/powerquicc
| successor        = 
| successor link   = 
}}
'''QorIQ''' (pronounced "''Core IQ''") is a family of [[ARM]] and [[POWER]] embedded and networking microprocessors designed and sold by [[NXP]] (formerly [[Freescale]]) since [[2008]] as a successor to the {{freescale|PowerQUICC}} family.

== Overview ==
Introduced in 2008 by [[Freescale]] as a successor to the {{freescale|PowerQUICC}} family, then one of industry's most popular communications processors. Like the PowerQUICC brand, QorIQ spanned the entire range of products from low-power and low-cost to large multi-core designs. Original designs were based on the [[POWER]] architecture. In 2012 Freescale announced the Layerscape series that adopts the [[ARM]] architecture which Freescale/NXP has been using since.

=== Identification ===
Only applies to original QorIQ P & T series:
{{chip identification
| parts     = 6
| ex 1      = QorIQ
| ex 2      = &nbsp;&nbsp;
| ex 3      = P
| ex 4      = 4
| ex 5      = 08
| ex 6      = 0
| ex 2 1    = QorIQ
| ex 2 2    = &nbsp;&nbsp;
| ex 2 3    = P
| ex 2 4    = 1
| ex 2 5    = 01
| ex 2 6    = 3
| desc 1    = '''Brand Name''' <br><table><tr><td style="width: 50px;">'''QorIQ'''</td><td></td></tr></table>
| desc 2    = 
| desc 3    = '''[[Technology Node]]'''<br><table><tr><td style="width: 50px;">'''P'''</td><td>[[45 nm process]]</td></tr><tr><td>'''T'''</td><td>[[28 nm process]]</td></tr></table>
| desc 4    = '''Platform Level'''
| desc 5    = '''[[Core Count]]'''<br><table><tr><td style="width: 50px;">'''01'''</td><td>[[single-core]]</td></tr><tr><td>'''02'''</td><td>[[dual-core]]</td></tr><tr><td>'''04'''</td><td>[[quad-core]]</td></tr><tr><td>'''08'''</td><td>[[octa-core]]</td></tr></table>
| desc 6    = '''Iteration/Version'''
}}

== Series ==
{{expand section}}

=== P Series ===
Announced in mid-2008, the QorIQ P-series are [[POWER]]-based microprocessors based on the {{freescale|e500|l=arch}} microarchitecture. Being the first Freescale multicore networking applications based on the [[45 nm process]], those parts offered a migration path for PowerQUICC II Pro and PowerQUICC III processor customers. All chips are fully software compatible with each other and existing PowerQUICC processors with multi-core parts supporting both symmetric and asymmetric multiprocessing.

==== P1 ====
The P1 series are designed for low-power fan-less design designed to succeed previous models (e.g., PowerQUICC II Pro) with higher performance at the same power envelope. P1 parts are designed for the applications such as Ethernet switch controllers, gateways, wireless LAN access points, network printing/storage, and other networking devices with tight thermal constraints.

==== P2 ====
The P2 series are designed to succeed the PowerQUICC III parts. These parts feature a large cache that may be configured as stashing memory, four Ethernet controllers with QoS features and flow control, DDR2/DDR3 SDRAM Controller with ECC support, four general purpose SerDes lanes that may be configured as either two Serial RapidIO ports, three PCI Express ports and two SGMII ports.

== See also ==
* [[Cavium]] {{cavium|ThunderX}}
* [[Intel]] {{intel|Atom}}
designer	Freescale + and NXP +
first announced	June 16, 2008 +
first launched	June 16, 2008 +
full page name	nxp/qoriq +
instance of	system on a chip family +
main designer	Freescale +
manufacturer	TSMC + and IBM +
name	QorIQ +
process	45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +
technology	CMOS +
word size	32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) +