Editing intel/microarchitectures/kaby lake

{{intel title|Kaby Lake|arch}}
{{microarchitecture
|atype=CPU
|name=Kaby Lake
|designer=Intel
|manufacturer=Intel
|introduction=August 30, 2016
|process=14 nm
|cores=2
|cores 2=4
|type=Superscalar
|speculative=Yes
|renaming=Yes
|stages min=14
|stages max=19
|isa=x86-16
|isa 2=x86-32
|isa 3=x86-64
|extension=MOVBE
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AVX
|extension 11=AVX2
|extension 12=AES
|extension 13=PCLMUL
|extension 14=FSGSBASE
|extension 15=RDRND
|extension 16=FMA3
|extension 17=F16C
|extension 18=BMI
|extension 19=BMI2
|extension 20=VT-x
|extension 21=VT-d
|extension 22=TXT
|extension 23=TSX
|extension 24=RDSEED
|extension 25=ADCX
|extension 26=PREFETCHW
|extension 27=CLFLUSHOPT
|extension 28=XSAVE
|extension 29=SGX
|extension 30=MPX
|l1i=32 KiB
|l1i per=core
|l1i desc=8-way set associative
|l1d=32 KiB
|l1d per=core
|l1d desc=8-way set associative
|l2=256 KiB
|l2 per=core
|l2 desc=4-way set associative
|l3=2 MiB
|l3 per=core
|l3 desc=Up to 16-way set associative
|side cache=64 MiB
|side cache per=package
|side cache desc=on Iris Plus GPUs only
|core name=Kaby Lake Y
|core name 2=Kaby Lake U
|core name 3=Kaby Lake H
|core name 4=Kaby Lake R
|core name 5=Kaby Lake S
|core name 6=Kaby Lake DT
|core name 7=Kaby Lake X
|predecessor=Skylake
|predecessor link=intel/microarchitectures/skylake
|successor=Coffee Lake
|successor link=intel/microarchitectures/coffee lake
|successor 2=Cannonlake
|successor 2 link=intel/microarchitectures/cannonlake
|pipeline=Yes
|OoOE=Yes
|issues=5
|core names=Yes
}}
[[File:7th Gen Core-i7-badge.png|thumb|right|175px|Kaby Lake is Intel's 7th Generation {{intel|Core i7}} MPUs.]]
'''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\|Cannonlake}} was originally set to replace {{\\|Skylake}} as the next microarchitecture using a [[10 nm process]], however Intel later revised their roadmap to include Kaby Lake (with Cannonlake being pushed back to [[2017]]). 

For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For workstation class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v6}}. There are no Kaby Lake-based server microprocessors.

== Codenames ==
{| class="wikitable"
|-
! Core !! Abbrev !! Description !! Graphics !! Target
|-
| {{intel|Kaby Lake Y|l=core}} || KBL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks
|-
| {{intel|Kaby Lake U|l=core}} || KBL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
|-
| {{intel|Kaby Lake R|l=core}} || KBL-R || Ultra-low Power || GT2 || Kaby Lake U Refresh
|-
| {{intel|Kaby Lake H|l=core}} || KBL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations
|-
| {{intel|Kaby Lake S|l=core}} || KBL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis
|-
| {{intel|Kaby Lake G|l=core}} || KBL-G || ||  || Kaby Lake + ?
|-
| {{intel|Kaby Lake X|l=core}} || KBL-X || Extreme Performance || || High-end desktops & enthusiasts market
|-
| {{intel|Kaby Lake DT|l=core}} || KBL-DT || Workstation || GT2 || Workstations & entry-level servers
|}

== Brands ==
Intel released Kaby Lake under 6 main brand families:

{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
|-
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features
|-
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
|-
| [[File:intel celeron (2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || style="text-align: left;" | Entry-level Budget || [[dual-core|dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}}
|-
| rowspan="2" | [[File:intel pentium (2015).png|50px|link=intel/pentium_(2009)]] || rowspan="2" | {{intel|Pentium (2009)|Pentium}} || style="text-align: left;" | Budget (Mobile) || rowspan="2" | dual || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}}
|-
| style="text-align: left;" | Budget (Desktop) || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}}
|-
| rowspan="2" | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || rowspan="2" |  {{intel|Core i3}} || style="text-align: left;" | Low-end Performance || rowspan="2" |  dual || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}}
|-
| style="text-align: left;" | Low-end Performance (E Series) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}}
|-
| rowspan="3" | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || rowspan="3" | {{intel|Core i5}} || rowspan="2" style="text-align: left;" | Mid-range Performance || dual || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
|-
| rowspan="2" | [[quad-core|quad]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
|-
| style="text-align: left;" | Mid-range Performance ({{intel|Kaby Lake R|KBL-R|l=core}}) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
|-
| rowspan="2" | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || rowspan="2" | {{intel|Core i7}} || rowspan="2" style="text-align: left;" | High-end Performance || dual || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
|-
|quad || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
|-
| [[File:xeon logo (2015).png|50px|link=intel/xeon e3]] ||  {{intel|Xeon E3}} || style="text-align: left;" | Workstation high-performance/dense servers || quad || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} 
|}

== Release Dates ==
Kaby Lake is set to be released in two phases. The first phase was announced in August of [[2016]] and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|l=core}} CPUs. Intel released mainstream {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|l=core}} processors on January 3, [[2017]] in time for CES 2017. The enthusiasts version, {{intel|Kaby Lake X|l=core}}, was introduced during Computex Taipei 2017.

On August 21 2017, Intel introduced 8th generation mobile processors ({{intel|Kaby Lake R|Kaby Lake Refresh|l=core}}) which is also based on the Kaby Lake microarchitecture and doubles the core (4 from 2) of many mainstream mobile microprocessors.

== Process Technology ==
{| class="wikitable" style="float: right;"
! colspan="2" | 14 nm Manufacturing Fabs
|-
! Fab !! Location
|-
| D1X || Hillsboro, Oregon
|-
| D1D || Hillsboro, Oregon
|-
| D1C || Hillsboro, Oregon
|-
| Fab 32 || Chandler, Arizona
|-
| Fab 24 || Leixlip, Ireland
|}
{{see also|intel/microarchitectures/broadwell#Process_Technology|14 nm lithography process|l1=Broadwell § Process Technology}}
Kaby Lake uses a modified and improved [[14 nm process]] used for the Broadwell microarchitecture (And {{\\|Skylake}}). Intel calls the modified process "14nm+". The new process has improved [[transistor]] channel strain. The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). These changes allowed Intel to increase the maximum frequencies of all models by around 100 to 300 [[megahertz]] which gives many [[single-thread]] applications a modest performance increase. Overall transistors improvement allowed for +12% drive current.

[[File:intel 14nm+ (nmos).png|400px]]
[[File:intel 14nm+ (pmos).png|400px]]

== Compatibility ==
There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. Microsoft announced that only [[Windows 10]] will have support for Kaby Lake. [[Linux]] added initial support for Kaby Lake starting with Linux Kernel 4.5.

{| class="wikitable"
! Vendor !! OS  !! Version !! Notes
|-
| rowspan="3" | Microsoft || rowspan="3" | Windows || style="background-color: #ffdad6;" | Windows 7 || No Support
|-
| style="background-color: #ffdad6;" | Windows 8 || No Support
|-
| style="background-color: #d6ffd8;" | Windows 10 || Support
|- 
| Linux || Linux || style="background-color: #d6ffd8;" | Kernel 4.5 || Initial Support (Fedora 24, Yocto v2.2, ..)
|-
| Google || Chromium || style="background-color: #d6ffd8;" | Chromium || Support
|-
| Wind River || VxWorks || style="background-color: #d6ffd8;" | VxWorks 7 || Support
|}

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[GCC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[LLVM]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code>
|}

=== CPUID ===
{| class="wikitable tc1 tc2 tc3 tc4"
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
|-
| rowspan="2" | {{intel|Kaby Lake Y|Y|l=core}}/{{intel|Kaby Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xE
|-
| colspan="4" | Family 6 Model 142
|-
| rowspan="2" | {{intel|Kaby Lake DT|DT|l=core}}/{{intel|Kaby Lake H|H|l=core}}/{{intel|Kaby Lake S|S|l=core}}/{{intel|Kaby Lake X|X|l=core}} || 0 || 0x6 || 0x9 || 0xE
|-
| colspan="4" | Family 6 Model 158
|}

== Architecture ==
{{see also|intel/microarchitectures/skylake#Key_changes_from_Broadwell|l1=Skylake § Key changes from Broadwell}}
While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of enhancements in Kaby Lake. Note that because of the improvements done to the process and the uplift in binning, it is the mostly the ultra-low power (i.e. mobile) processors that will see the most substantial gain. Likewise, the high-end models will see very little gain. The enhanced manufacturing process allowed Kaby Lake chips to be highly [[overclockable]] with models such as the [[Core i7-7700K]] capable of comfortably reaching 5 GHz for many people with a reasonable cooling setup.

=== Key changes from {{\\|Skylake}} ===
* Enhanced "14nm+" process results in ~15% higher frequency (100 to 300 MHz increase across the board, same price)
* Same IPC as Skylake (i.e. performance/[[MHz]] is unchanged)
* 10x performance/[[Watt]] over {{\\|Nehalem}} (Up from 8x)
* [[intel/microarchitectures/skylake#.22Speed_Shift.22_.28new_power_management.29|SkyLake's Speed Shift]] implementation is significantly improved, cutting responsiveness by as much as 66% (down to just ~10-15ms to peak frequency).

* Mainstream chipset (See [[#Sockets.2FPlatform|§ Sockets]])
** {{intel|Sunrise Point|l=chipset}} (100 series) → {{intel|Union Point|l=chipset}} (200 Series)
*** Sunrise Point is still compatible (may need firmware update)
** Added support for {{intel|Optane}} Technology

* Memory
** Faster memory for mainstream desktops (i.e., {{intel|Kaby Lake S|l=core}}) DDR4-2400 (from DDR4-2133)
** Faster memory for high-ferf mobile (i.e., {{intel|Kaby Lake H|l=core}}) DDR4-2400 (from DDR4-2133)

* Interfaces
** [[Embedded DisplayPort]] ([[eDP]]) now supports eDP Standard 1.4 (From 1.3 in Skylake)

* {{intel|Gen 9.5|l=arch}} GPUs
** Iris Plus now support HDMI (1.4a) 4096x2304 @ 30 Hz (from 24 Hz) 
** New native hardware support for 4K HEVC/VP9 (See [[#Graphics|§ Graphics]])
** {{intel|HD Graphics 510}} '''→''' {{intel|HD Graphics 610}} (12 Execution Units, no change)
** {{intel|HD Graphics 515}} '''→''' {{intel|HD Graphics 615}} (24 Execution Units, no change)
** {{intel|HD Graphics 520}} '''→''' {{intel|HD Graphics 620}} (24 Execution Units, no change)
** {{intel|HD Graphics 530}} '''→''' {{intel|HD Graphics 630}} (24 Execution Units, no change)
** {{intel|HD Graphics P530}} '''→''' {{intel|HD Graphics P630}} (24 Execution Units, no change)
** {{intel|Iris Graphics 540}} '''→''' {{intel|Iris Plus Graphics 640}} (48 Execution Units, no change)
** {{intel|Iris Graphics 550}} '''→''' {{intel|Iris Plus Graphics 650}} (48 Execution Units, no change)

* Families
** {{intel|Core i3}} processors dropped support for ECC memory (except for Embedded models)
** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.)
** {{intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support

=== Block Diagram ===

====== Entire SoC Overview (dual) ======
[[File:kaby lake soc block diagram (dual).svg|800px]]

==== Entire SoC Overview (quad) ====
[[File:kaby lake soc block diagram.svg|900px]]

==== Individual Core ====
<small>(Core identical to {{\\|Skylake (client)}})</small>

[[File:skylake block diagram.svg|900px]]

==== Gen9.5 ====
See {{intel|Gen9.5#Gen9.5|l=arch}}.

=== Memory Hierarchy ===
The overall memory structure is identical to {{\\|Skylake}}.

<!-- ===================== START IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
* Cache
** L0 µOP cache:
*** 1,536 µOPs, 8-way set associative
**** 32 sets, 6-µOP line size
**** statically divided between threads, per core, inclusive with L1I
** L1I Cache:
*** 32 [[KiB]], 8-way set associative
**** 64 sets, 64 B line size
**** shared by the two threads, per core
** L1D Cache:
*** 32 KiB, 8-way set associative
*** 64 sets, 64 B line size
*** shared by the two threads, per core
*** 4 cycles for fastest load-to-use (simple pointer accesses)
**** 5 cycles for complex addresses
*** 64 B/cycle load bandwidth
*** 32 B/cycle store bandwidth
*** Write-back policy
** L2 Cache:
*** Unified, 256 KiB, 4-way set associative
*** Non-inclusive
*** 1024 sets, 64 B line size
*** 12 cycles for fastest load-to-use
*** 64 B/cycle bandwidth to L1$
*** Write-back policy
** L3 Cache/LLC:
*** Up to 2 MiB Per core, shared across all cores
*** Up to 16-way set associative
*** Inclusive
*** 64 B line size
*** Write-back policy
*** Per each core:
**** Read: 32 B/cycle (@ ring [[clock]])
**** Write: 32 B/cycle (@ ring clock)
*** 42 cycles for fastest load-to-use
** Side Cache:
*** 64 MiB & 128 MiB [[eDRAM]]
*** Per package
*** Only on the Iris Pro GPUs
*** Read: 32 B/cycle (@ [[eDRAM]] clock)
*** Write: 32 B/cycle (@ eDRAM clock)
** System [[DRAM]]:
*** 2 Channels
*** 8 B/cycle/channel (@ memory clock)
*** 42 cycles + 51 ns latency

Kaby Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
* TLBs:
** ITLB
*** 4 KiB page translations:
**** 128 entries; 8-way set associative
**** dynamic partitioning
*** 2 MiB / 4 MiB page translations:
**** 8 entries per thread; fully associative
**** Duplicated for each thread
** DTLB
*** 4 KiB page translations:
**** 64 entries; 4-way set associative
**** fixed partition
*** 2 MiB / 4 MiB page translations:
**** 32 entries; 4-way set associative
**** fixed partition
*** 1G page translations:
**** 4 entries; fully associative
**** fixed partition
** STLB
*** 4 KiB + 2 MiB page translations:
**** 1536 entries; 12-way set associative
**** fixed partition
*** 1 GiB page translations:
**** 16 entries; 4-way set associative
**** fixed partition
<!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->

== Core ==
=== Pipeline ===
{{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}}
Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}.

==== Scheduler Ports & Execution Units ====
<table class="wikitable">
<tr><th colspan="2">Scheduler Ports Designation</th></tr>
<tr><th rowspan="5">Port 0</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and String ops</td></tr>
<tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr>
<tr><td>Integer/FP Division and [[Square Root]]</td></tr>
<tr><td>[[AES]] Encryption</td></tr>
<tr><td>Branch2</td></tr>
<tr><th rowspan="2">Port 1</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and Bit Scanning</td></tr>
<tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr>
<tr><th rowspan="3">Port 5</th><td>Integer/Vector Arithmetic, Logic</td></tr>
<tr><td>Vector Permute</td></tr>
<tr><td>[[x87]] FP Add, Composite Int, CLMUL</td></tr>
<tr><th rowspan="2">Port 6</th><td>Integer Arithmetic, Logic, Shift</td></tr>
<tr><td>Branch</td></tr>
<tr><th>Port 2</th><td>Load, AGU</td></tr>
<tr><th>Port 3</th><td>Load, AGU</td></tr>
<tr><th>Port 4</th><td>Store, AGU</td></tr>
<tr><th>Port 7</th><td>AGU</td></tr>
</table>

{| class="wikitable collapsible collapsed"
|-
! colspan="3" | Execution Units 
|-
! Execution Unit !! # of Units !! Instructions
|-
| ALU || 4 || add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup*
|-
| DIV || 1 || divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv
|-
| Shift || 2 || sal, shl, rol, adc, sarx, adcx, adox, etc...
|-
| Shuffle || 1 || (v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*, vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw
|-
| Slow Int || 1 || mul, imul, bsr, rcl, shld, mulx, pdep, etc...
|-
| Bit Manipulation || 2 || andn, bextr, blsi, blsmsk, bzhi, etc
|-
| FP Mov || 1 || (v)movsd/ss, (v)movd gpr
|-
| SIMD Misc || 1 || STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm
|-
| Vec ALU || 3 || (v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*, (v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd
|-
| Vec Shift || 2 || (v)psllv*, (v)psrlv*, vector shift count in imm8
|-
| Vec Add || 2 || (v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si
|-
| Vec Mul || 2 || (v)mul*, (v)pmul*, (v)pmadd*
|-
|colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included.
|}

== Graphics ==
{{main|intel/microarchitectures/gen9.5|l1=Gen9.5}}
Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, an [[Embedded DisplayPort]] (eDP) 1.4 interfaces. Kaby Lake's biggest enhancement is the addition of native [[fixed function]] HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as [[fixed function]] HEVC/VP9 encoding for 4K (8-bit).

{| class="wikitable tc2 tc3"
|-
! colspan="5" | [[Integrated Graphics Processor]] !! colspan="9" | Standards
|-
! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !!  rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]]
|-
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
|-
| {{intel|HD Graphics 610}} || 12 || GT1 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake U|U}} || - || rowspan="7" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="7" style="text-align: center;" | '''12''' || rowspan="7" style="text-align: center;" | '''N/A''' || rowspan="7" style="text-align: center;" | '''5.1''' || rowspan="7" style="text-align: center;" | '''4.5''' || rowspan="7" style="text-align: center;" | '''4.5''' || rowspan="7" style="text-align: center;"  colspan="1" | '''2.1''' || style="text-align: center;" rowspan="7" | '''2.0'''
|-
| {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || -
|-
| {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U}} || -
|-
| {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || -
|-
| {{intel|HD Graphics P630}} || 24 || GT2 || {{intel|Kaby Lake H|H}} || -
|-
| {{intel|Iris Plus Graphics 640}} || 48 || GT3e|| {{intel|Kaby Lake U|U}} || 64 MiB
|-
| {{intel|Iris Plus Graphics 650}} || 48 || GT3e || {{intel|Kaby Lake U|U}} || 64 MiB
|}

<references group=graphics />
==== Hardware Accelerated Video ====
{{kaby lake hardware accelerated video table}}

== Sockets/Platform ==
{{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|U|l=core}} are single-chip solutions. {{intel|Kaby Lake Y|Y|l=core}} chips utilize a 2-die [[multi-chip package]] (MCP) whereas the {{intel|Kaby Lake U|l=core}}'s are either 2 or 3-die MCP configuration. The 3 die chip configuration are for the Iris [[IGP]]s which incorporate an on-package cache (OPC) in addition to the hub. Communication from the CPU to the hub on those chips are done via a lightweight On-Package Interconnect (OPI) interface. {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|H|l=core}} are a two-chip solution linked together via Intel's standard [[DMI 3.0]] bus interface which utilizes 4 of the CPU's 20 [[PCIe]] 3.0 lanes (having a transfer rate of 8 GT/s per lane). Only {{intel|Kaby Lake S|l=core}} (used on mainstream desktop processors) are not soldered onto the [[motherboard]] and can be interchanged/replaced.
{| class="wikitable" style="text-align: center;"
|-
! !! Core !! Socket !! Permanent !! Platform !! Chipset !! Bus
|-
| [[File:kaby lake y (back).png|100px|link=intel/cores/kaby_lake_y]] || {{intel|Kaby Lake Y|l=core}} || {{intel|BGA-1515}} || Yes || 1-chip || rowspan="3" | N/A || rowspan="3" | OPI
|-
| [[File:kaby lake u (back; standard).png|100px|link=intel/cores/kaby_lake_u]] || {{intel|Kaby Lake U|l=core}} || rowspan="2" | {{intel|BGA-1356}} || rowspan="2" | Yes || rowspan="2" | 1-chip
|-
| [[File:kaby lake r (back).png|100px|link=intel/cores/kaby_lake_r]] || {{intel|Kaby Lake R|l=core}}
|-
| [[File:kaby lake h (back).png|100px|link=intel/cores/kaby_lake_h]] || {{intel|Kaby Lake H|l=core}} || {{intel|BGA-1440}} || Yes || 2-chip || rowspan="2" | {{intel|Sunrise Point}}<ref group="c">Requires a firmware update in order to work with Kaby Lake chips</ref><br>{{intel|Union Point}} || rowspan="4" | [[DMI 3.0]]
|-
| rowspan="2" | [[File:kaby lake s (back).png|100px|link=intel/cores/kaby_lake_s]] || {{intel|Kaby Lake S|l=core}} || {{intel|LGA-1151}} || No || 2-chip 
|-
| {{intel|Kaby Lake DT|l=core}} || {{intel|LGA-1151}} || No || 2-chip || Xeon {{intel|Sunrise Point}}<br>Xeon {{intel|Union Point}}
|-
| [[File:skylake x (back).png|100px|link=intel/cores/kaby_lake_x]] || {{intel|Kaby Lake X|l=core}} || {{intel|LGA-2066}} || No || 2-chip || {{intel|Lewisburg}}
|}

<references group="c" />


=== Packages ===
{| class="wikitable"
|-
! Core !! Die Type !! Package !! Dimensions
|-
| {{intel|Kaby Lake H|l=core}} || 4+2 || rowspan="2" | {{intel|FCBGA-1440}} || rowspan="2" | 42 mm x 28 mm x 1.46 mm
|-
| {{intel|Kaby Lake H|l=core}} || 2+2
|-
| {{intel|Kaby Lake S|l=core}} || 4+2 || rowspan="2" | {{intel|FCLGA-1151}} || rowspan="2" | 37.5 mm x 37.5 mm x 4.4 mm
|-
| {{intel|Kaby Lake S|l=core}} || 2+2
|}

== Clock domains ==
Kaby Lake is divided into a number of [[clock domains]], each controlling the clock frequency of their respective unit in the processor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]).

* '''BCLK''' - Bus/Base Clock - The  system bus interface frequency (once upon a time referred to the actual [[FSB]] speed, it now serves as only a base clock reference for all other clock domains). The base clock is 100 MHz.
* '''Core Clock''' - The frequency at which the core and the [[L1]]/[[L2]] caches operate at. (Frequency depends on the model and is represented as a multiple of BCLK).
* '''Ring Clock''' - The frequency at which the ring interconnect and [[L3$|LLC]] operate at. Data from/to the individual cores are read/written into the L3 at a rate of 32B/cycle operating at Ring Clock frequency.
* '''IGP Clock''' - The frequency at which the [[integrated graphics]] ({{\\|Gen9}} GPU) operates at. Data from/to the GPU are read/written into the LLC at a rate of 64B/cycle operating at this frequency as well.
* '''eDRAM Clock''' - The frequency at which the [[embedded DRAM]] operates at (only available for certain models). Data is read/written from/to the LLC at a rate of 32B/cycle operating at this frequency as well.
* '''MemClk''' - Memory Clock - The frequency at which the system DRAM operates at. DRAM data is transfered at a rate of 8B/cycle operating at MemClk frequency.

[[File:kaby lake soc clock domain block diagram.svg|850px]]

=== Overclocking ===
See {{intel|Skylake#Overclocking|Skylake §Overclocking|l=arch}}.

== Die ==
Kaby Lake desktop and mobile come and [[2 cores|2]] and [[4 cores|4]] cores. Each variant has its own die. One of the most noticeable changes on die is the amount of die space allocated to the [[GPU]]. The major components of the die are:

* System Agent
* CPU Core
* Ring bus interconnect
* Memory Controller

=== System Agent ===
The System Agent (SA) contains the Image Processing Unit (IPU), the Display Engine (DE), and the I/O bus. Note that the mainstream desktop (i.e., [[quad-core]] die) does not have an IPU (The memory controller actually occupies a portion of where it would otherwise be).

<div>
<div style="text-align: center; display: inline-block;">
'''Dual-Core Die'''
<div style="float: left;  margin: 10px;">[[File:kaby lake 2c sa.png|150px]]</div>
<div style="float: left;  margin: 10px;">[[File:kaby lake 2c sa (annotated).png|150px]]</div>
</div> 
<div style="text-align: center; display: inline-block;">
'''Quad-Core Die'''
<div style="float: left;  margin: 10px;">[[File:kaby lake 4c sa.png|150px]]</div>
<div style="float: left;  margin: 10px;">[[File:kaby lake 4c sa (annotated).png|150px]]</div>
</div> 
<div style="text-align: center; display: inline-block;">
'''Quad-Core ({{intel|Kaby Lake R|l=core}}) Die'''
<div style="float: left;  margin: 10px;">[[File:kaby lake r sa.png|150px]]</div>
<div style="float: left;  margin: 10px;">[[File:kaby lake r sa (annotated).png|150px]]</div>
</div> 
</div>
{{clear}}

=== Integrated Graphics ===
The [[integrated graphics]] takes up the largest portion of the die. The normal [[dual-core]] and [[quad-core]] dies come with 24 EU {{\\|Gen9.5}} GPU (with 12 units disabled on the low end models).

<div style="text-align: center; display: inline-block;">
<div style="float: left;  margin: 10px;">[[File:kaby lake gpu.png|400px]]</div>
<div style="float: left;  margin: 10px;">[[File:kaby lake gpu (annotated).png|450px]]</div>
</div>

==== Layout Difference from Skylake ====
The majority of the enhancements to Kaby Lake comes from the Unslice portion of the {{\\|Gen9.5}} integrated GPU. The shaded region marked in green indicates new/modified physical layout changes. The rest of the die, shaded in red, is unchanged from {{\\|Skylake}}.

[[File:kaby lake skylake gpu diff.png|450px]]

=== Dual-Core ===
Die shot of the [[dual-core]] {{\\|Gen9.5|GT2}} Kaby Lake processors. Those are found in mobile models, and entry-level/budget processors:

* [[14 nm process|14 nm+ process]]
* 11 metal layers
* 2 CPU cores + 24 GPU EUs

: [[File:kaby lake (dual core).png|650px]]


: [[File:kaby lake (dual core) (annotated).png|650px]]

=== Quad-Core ===
Die shot of the [[quad-core]] {{\\|Gen9.5|GT2}} Kaby Lake processors. Those are found in almost all mainstream desktop processors.

* [[14 nm process|14 nm+ process]]
* 11 metal layers
* ~126 mm² die size
* 4 CPU cores + 24 GPU EUs

: [[File:kaby lake (quad core).png|650px]]


: [[File:kaby lake (quad core) (annotated).png|650px]]

=== Quad-Core (Mobile {{intel|Kaby Lake R|l=core}}) ===
With the introduction of {{intel|Kaby Lake R|l=core}}, a new quad-core die was introduced with the IPU in the System Agent.

* [[14 nm process|14 nm+ process]]
* 11 metal layers
* 123 mm² die size
* 4 CPU cores + 24 GPU EUs

: [[File:kaby lake r die shot.png|650px]]


: [[File:kaby lake r die shot (annotated).png|650px]]

=== Additional Shots ===
Additional die and wafer shots provided by Intel:

<gallery mode=slideshow>
File:kaby lake silicon wafer.jpg|Kaby Lake silicon [[wafer]] with 7th generation core processor dies.
File:intel kaby lake r wafer.png|Wafer shot of {{intel|Kaby Lake R|l=core}}, 8th generation core.
</gallery>

== All Kaby Lake Chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="25">Kaby Lake Chips</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan="9">Major Feature Diff</th></tr>
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number">Cores</th><th data-sort-type="number">Threads</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>[[ECC]]</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr>
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Uniprocessors]]</th></tr>
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::!Kaby Lake R]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?platform
 |?core name
 |?core count
 |?thread count
 |?l3$ size
 |?l4$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |?has_ecc_memory_support
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |?has advanced vector extensions
 |?has advanced vector extensions 2
 |?has intel trusted execution technology
 |?has transactional synchronization extensions
 |?has intel vpro technology
 |?has_intel_vt-d_technology
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=27:19
 |mainlabel=-
 |limit=100
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">8th Generation ({{intel|Kaby Lake R|Kaby Lake Refresh|l=core}})</th></tr>
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::Kaby Lake R]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?platform
 |?core name
 |?core count
 |?thread count
 |?l3$ size
 |?l4$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |?has_ecc_memory_support
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |?has advanced vector extensions
 |?has advanced vector extensions 2
 |?has intel trusted execution technology
 |?has transactional synchronization extensions
 |?has intel vpro technology
 |?has_intel_vt-d_technology
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=27:19
 |mainlabel=-
 |limit=100
}}
{{comp table count|ask=[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Kaby Lake]]}}
</table>
{{comp table end}}

== Documents ==
=== 7th Generation ===
* [[:File:7th-gen-intel-core-january-product-brief.pdf|7th gen intel core & Intel Xeon processor briefing]]
* [[:File:7th Generation Intel® Core™ Processor Product Brief.pdf|7th Generation Intel Core Processor Product Brief]]
* [[:File:7th-gen-intel-core-january-fact-sheet.pdf|7th Gen Intel Core & Xeon Processor Family Fact Sheet]]
* [[:File:7th-gen-intel-core-vpro-product-brief.pdf|7th Generation Intel Core vPro Processor Briefing]]
* [[:File:7th Generation Intel® Core™ Processor Y-Series and U-Series Product Brief.pdf|7th Generation Intel Core Processor Y-Series and U-Series Product Brief]]
* [[:File:7th Gen Intel® Core™ Processor Family Fact Sheet.pdf|7th Gen Intel Core Processor Family Fact Sheet]]
* [[:File:7th-generation-core-processor-deskop-iot-platform-brief.pdf|7th Generation Intel Core Processor-Based Platforms for Internet of Things (IoT) Solutions Platform brief]]
* [[:File:how-to-watch-4k-uhd-premium-content-with-your-pc.pdf|HOW TO WATCH 4K ULTRA HD (UHD) PREMIUM CONTENT WITH YOUR PC]]
=== 8th Generation ===
* [[:File:kaby-lake-r-product-brief.pdf|Kaby Lake R Product Brief]]

== References ==
* Intel Developer Forum 2015, San Francisco, August 18-20, 2015
* Intel Technology and Manufacturing Day, March 28, 2017

== Artwork ==
<gallery>
File:7th Gen Intel Core i3 unlocked box.png|Kaby Lake offers the first unlocked {{intel|Core i3}} model.
File:7th Gen Intel Core i7 unlocked box - front.png
File:7th Gen Intel Core i7 unlocked box - back.png
File:7th Gen Intel Core family.jpg
File:7th Gen-Navoy-1.JPG|Navin Shenoy, Intel corporate vice president and general manager for its Client Computing Group
File:7th Gen-Navoy-2.JPG
File:7th Gen-Navoy-3.JPG
File:7th Gen-Walker-1.JPG|Chris Walker, Intel vice president for its Client Computing Group and general manager of notebook product marketing
File:7th Gen-Walker-2.JPG
File:7th Gen-Walker-3.JPG
File:7th Gen-water-1.JPG
File:7th-gen-wafer.jpg|7th gen core silicon wafers
</gallery>

== External Links ==
* [https://www.youtube.com/watch?v=3zoD3_ZZeaw Kaby Lake – All CPUs Benchmarks ROUNDUP]

== See also ==
* {{amd|microarchitectures/zen|AMD's Zen}}
codename	Kaby Lake +
core count	2 + and 4 +
designer	Intel +
first launched	August 30, 2016 +
full page name	intel/microarchitectures/kaby lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Kaby Lake +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	14 nm (0.014 μm, 1.4e-5 mm) +