Editing intel/xeon gold/5122

{{intel title|Xeon Gold 5122}}
{{mpu
|name=Xeon Gold 5122
|image=skylake sp (basic).png
|designer=Intel
|manufacturer=Intel
|model number=5122
|part number=BX806735122
|part number 2=CD8067303330702
|s-spec=SR3AT
|s-spec qs=QMRN
|market=Server
|first announced=April 25, 2017
|first launched=July 11, 2017
|release price=$1221.00
|family=Xeon Gold
|series=5000
|locked=Yes
|frequency=3,600 MHz
|turbo frequency1=3,700 MHz
|clock multiplier=36
|cpuid=0x50654
|isa=x86-64
|isa family=x86
|microarch=Skylake (server)
|platform=Purley
|chipset=Lewisburg
|core name=Skylake SP
|core family=6
|core stepping=H0
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=4
|thread count=8
|max cpus=4
|max memory=768 GiB
|tdp=105 W
|tcase min=0 °C
|tcase max=71 °C
|package module 1={{packages/intel/fclga-3647}}
}}
'''Xeon Gold 5122''' is a {{arch|64}} [[quad-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5122, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.6 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.

== Cache ==
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
The Xeon Gold 5122 features a considerably larger non-default 16.5 MiB of [[L3]], a size that would normally be found on a 12-core part.
{{cache size
|l1 cache=256 KiB
|l1i cache=128 KiB
|l1i break=4x32 KiB
|l1i desc=8-way set associative
|l1d cache=128 KiB
|l1d break=4x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=4 MiB
|l2 break=4x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=16.5 MiB
|l3 break=12x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2400
|ecc=Yes
|max mem=768 GiB
|controllers=2
|channels=6
|max bandwidth=107.3 GiB/s
|bandwidth schan=17.88 GiB/s
|bandwidth dchan=35.76 GiB/s
|bandwidth qchan=71.53 GiB/s
|bandwidth hchan=107.3 GiB/s
}}

== Expansions ==
{{expansions
| pcie revision      = 3.0
| pcie lanes         = 48
| pcie config        = x16
| pcie config 2      = x8
| pcie config 3      = x4
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes
|avx512f=Yes
|avx512cd=Yes
|avx512er=No
|avx512pf=No
|avx512bw=Yes
|avx512dq=Yes
|avx512vl=Yes
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx5124vnniw=No
|avx512vpopcntdq=No
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|tbt1=No
|tbt2=Yes
|tbmt3=No
|bpt=No
|eist=Yes
|sst=Yes
|flex=No
|fastmem=No
|ivmd=Yes
|intelnode=Yes
|kpt=Yes
|ptt=Yes
|mbe=Yes
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=Yes
|txt=Yes
|ht=Yes
|vpro=Yes
|vtx=Yes
|vtd=No
|ept=Yes
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
}}

== Frequencies ==
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
{{frequency table
|freq_base=3,600 MHz
|freq_1=3,700 MHz
|freq_2=3,700 MHz
|freq_3=3,700 MHz
|freq_4=3,700 MHz
|freq_avx2_base=3,300 MHz
|freq_avx2_1=3,600 MHz
|freq_avx2_2=3,600 MHz
|freq_avx2_3=3,600 MHz
|freq_avx2_4=3,600 MHz
|freq_avx512_base=2,700 MHz
|freq_avx512_1=3,500 MHz
|freq_avx512_2=3,500 MHz
|freq_avx512_3=3,300 MHz
|freq_avx512_4=3,300 MHz
}}

[[Category:microprocessor models by intel based on skylake extreme core count die]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5122 - Intel#io +
base frequency	3,600 MHz (3.6 GHz, 3,600,000 kHz) +
chipset	Lewisburg +
clock multiplier	36 +
core count	4 +
core family	6 +
core name	Skylake SP +
core stepping	H0 +
cpuid	0x50654 +
designer	Intel +
family	Xeon Gold +
first announced	April 25, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon gold/5122 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Transactional Synchronization Extensions +, Extended Page Tables + and Advanced Vector Extensions 512 +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	16-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description	11-way set associative +
l3$ size	16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldate	July 11, 2017 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	344.15 K (71 °C, 159.8 °F, 619.47 °R) +
max cpu count	4 +
max dts temperature	104 °C +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature	0 °C +
model number	5122 +
name	Xeon Gold 5122 +
number of avx-512 execution units	2 +
package	FCLGA-3647 +
part number	CD8067303330702 + and BX806735122 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) +
s-spec	SR3AT +
s-spec (qs)	QMRN +
series	5100 +
smp interconnect	UPI +
smp interconnect links	3 +
smp interconnect rate	10.4 GT/s +
smp max ways	4 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technology	CMOS +
thread count	8 +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +