Editing renesas/r-car/e1

{{renesas title|R-Car E1}}
{{mpu
|name=R-Car E1
|no image=Yes
|designer=Renesas
|designer 2=ARM Holdings
|manufacturer=TSMC
|model number=E1
|part number=μPD35004
|market=Embedded
|first announced=August 25, 2011
|first launched=June, 2012
|release price=$30
|family=R-Car
|series=1st Gen
|frequency=533 MHz
|isa=ARMv7
|isa family=ARM
|microarch=Cortex-A9
|core name=Cortex-A9
|process=40 nm
|technology=CMOS
|word size=32 bit
|core count=1
|thread count=1
|max cpus=1
|max memory=1 GiB
|v core=1.1 V
|v io=3.3 V
|package module 1={{packages/renesas/fcbga-429}}
}}
'''R-Car E1''' is an entry-level performance embedded SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The E1 features a single {{armh|Cortex-A9|l=arch}} core operating at 533 MHz. This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX531}} [[GPU]] operating at 177 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.

== Cache ==
{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
{{cache size
|l1 cache=64 KiB
|l1i cache=32 KiB
|l1i break=1x32 KiB
|l1i desc=4-way set associative
|l1d cache=32 KiB
|l1d break=1x32 KiB
|l1d desc=4-way set associative
}}

== Memory controller ==
{{memory controller
|type=DDR3-1066
|type 2=DDR2-533
|ecc=No
|max mem=1 GiB
|controllers=1
|channels=1
|width=32 bit
|max bandwidth=1.99 GiB/s
|bandwidth schan=1.99 GiB/s
}}

== Expansions ==
{{expansions
| usb revision       = 2.0
| usb ports          = 2
| usb rate           = 480 Mbps
| uart               = Yes
| uart ports         = 8
| sata revision      = 3.0
| sata ports         = 1
| i2c                = Yes
| i2c ports          = 4
| gp io              = Yes
| jtag               = Yes
}}
* MLB (MOST150) 6-Pin I/F
* 2 x CAN 32 Message Buffers
* MMC
* 3 x SD

== Graphics ==
{{integrated graphics
| gpu                 = PowerVR SGX531
| designer            = Imagination Technologies
| execution units     = 1
| max displays        = 2
| frequency           = 177 MHz

| opengl es ver       = 2.0
}}

== Features == 
{{arm features
|thumb=No
|thumb2=Yes
|thumbee=Yes
|vfpv1=No
|vfpv2=No
|vfpv3=Yes
|vfpv3-d16=No
|vfpv3-f16=No
|vfpv4=No
|vfpv4-d16=No
|vfpv5=No
|neon=Yes
|jazelle=Yes
|wmmx=No
|wmmx2=No
}}

== Block Diagram ==
: [[File:r-car e1 block.png|650px]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	R-Car E1 - Renesas#package +
base frequency	533 MHz (0.533 GHz, 533,000 kHz) +
core count	1 +
core name	Cortex-A9 +
core voltage	1.1 V (11 dV, 110 cV, 1,100 mV) +
designer	Renesas + and ARM Holdings +
family	R-Car +
first announced	August 25, 2011 +
first launched	June 2012 +
full page name	renesas/r-car/e1 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	PowerVR SGX531 +
integrated gpu base frequency	177 MHz (0.177 GHz, 177,000 KHz) +
integrated gpu designer	Imagination Technologies +
integrated gpu execution units	1 +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	ARMv7 +
isa family	ARM +
l1$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description	4-way set associative +
l1d$ size	32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description	4-way set associative +
l1i$ size	32 KiB (32,768 B, 0.0313 MiB) +
ldate	June 2012 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory	1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
max memory bandwidth	1.99 GiB/s (2,037.76 MiB/s, 2.137 GB/s, 2,136.746 MB/s, 0.00194 TiB/s, 0.00214 TB/s) +
max memory channels	1 +
microarchitecture	Cortex-A9 +
model number	E1 +
name	R-Car E1 +
package	FCBGA-429 +
part number	μPD35004 +
process	40 nm (0.04 μm, 4.0e-5 mm) +
release price	$ 30.00 (€ 27.00, £ 24.30, ¥ 3,099.90) +
series	1st Gen +
smp max ways	1 +
supported memory type	DDR3-1066 + and DDR2-533 +
technology	CMOS +
thread count	1 +
word size	32 bit (4 octets, 8 nibbles) +