Editing renesas/r-car/m1a

{{renesas title|R-Car M1A}}
{{mpu
|name=R-Car M1A
|no image=Yes
|designer=Renesas
|designer 2=ARM Holdings
|manufacturer=TSMC
|model number=M1A
|part number=R8A77781
|market=Embedded
|first announced=February 16, 2011
|first launched=June, 2012
|release price=$75
|family=R-Car
|series=1st Gen
|frequency=800 MHz
|isa=ARMv7
|isa family=ARM
|isa 2=SuperH
|isa 2 family=SuperH
|microarch=Cortex-A9
|microarch 2=SH-4A
|core name=Cortex-A9
|core name 2=SH-4A
|process=40 nm
|technology=CMOS
|word size=32 bit
|core count=2
|thread count=2
|max memory=1 GiB
|v core=1.2 V
|v io=3.3 V
|package module 1={{packages/renesas/fcbga-472}}
}}
'''R-Car M1A''' is a mid-range performance embedded [[dual-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1A features a single {{armh|Cortex-A9|l=arch}} core and an additional {{renesas|SH-4A|l=arch}} core, both operating at 800 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory.

== Cache ==
{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
{{cache size
|l1 cache=128 KiB
|l1i cache=64 KiB
|l1i break=2x32 KiB
|l1i desc=4-way set associative
|l1d cache=64 KiB
|l1d break=2x32 KiB
|l1d desc=4-way set associative
}}

== Memory controller ==
{{memory controller
|type=DDR3-1066
|type=DDR2-800
|ecc=No
|max mem=1 GiB
|controllers=1
|channels=2
|width=32 bit
|max bandwidth=7.95 GiB/s
|bandwidth schan=3.97 GiB/s
|bandwidth dchan=7.95 GiB/s
}}

== Expansions ==
{{expansions
| usb revision       = 2.0
| usb ports          = 2
| usb rate           = 480 Mbps
| uart               = Yes
| uart ports         = 8
| sata revision      = 3.0
| sata ports         = 1
| i2c                = Yes
| i2c ports          = 4
| gp io              = Yes
| jtag               = Yes
}}
* MLB (MOST150) 6-Pin I/F
* 2 x CAN 32 Message Buffers
* MMC
* 3 x SD

== Graphics ==
* 20MPoly/s; 1000MPix/s; 3.2GFlops/s
{{integrated graphics
| gpu                 = PowerVR SGX540
| designer            = Imagination Technologies
| execution units     = 2
| max displays        = 2
| frequency           = 200 MHz

| opengl es ver       = 2.0
| opengl ver          = 2.1
}}

== Features == 
{{arm features
|thumb=No
|thumb2=Yes
|thumbee=Yes
|vfpv1=No
|vfpv2=No
|vfpv3=Yes
|vfpv3-d16=No
|vfpv3-f16=No
|vfpv4=No
|vfpv4-d16=No
|vfpv5=No
|neon=Yes
|jazelle=Yes
|wmmx=No
|wmmx2=No
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	R-Car M1A - Renesas#package +
base frequency	800 MHz (0.8 GHz, 800,000 kHz) +
core count	2 +
core name	Cortex-A9 + and SH-4A +
core voltage	1.2 V (12 dV, 120 cV, 1,200 mV) +
designer	Renesas + and ARM Holdings +
family	R-Car +
first announced	February 16, 2011 +
first launched	June 2012 +
full page name	renesas/r-car/m1a +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	PowerVR SGX540 +
integrated gpu base frequency	200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu designer	Imagination Technologies +
integrated gpu execution units	2 +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	ARMv7 + and SuperH +
isa family	ARM + and SuperH +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	4-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	4-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
ldate	June 2012 +
manufacturer	TSMC +
market segment	Embedded +
max memory	1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
max memory bandwidth	7.95 GiB/s (8,140.8 MiB/s, 8.536 GB/s, 8,536.248 MB/s, 0.00776 TiB/s, 0.00854 TB/s) +
max memory channels	2 +
microarchitecture	Cortex-A9 + and SH-4A +
model number	M1A +
name	R-Car M1A +
package	FCBGA-472 +
part number	R8A77781 +
process	40 nm (0.04 μm, 4.0e-5 mm) +
release price	$ 70.00 (€ 63.00, £ 56.70, ¥ 7,233.10) +
series	1st Gen +
supported memory type	DDR2-800 + and DDR3-1066 +
technology	CMOS +
thread count	2 +
word size	32 bit (4 octets, 8 nibbles) +