Editing cavium/octeon/cn3850-400bg1521-nsp

{{cavium title|CN3850-400 NSP}}
{{mpu
| name                = Cavium CN3850-400 NSP
| no image            = 
| image               = octeon cn38xx.png
| image size          = 
| caption             = 
| designer            = Cavium
| manufacturer        = TSMC
| model number        = CN3850-400 NSP
| part number         = CN3850-400BG1521-NSP
| part number 2       = 
| part number 3       = 
| part number 4       = 
| market              = Networking
| first announced     = September 13, 2004 
| first launched      = June 1, 2005
| last order          = 
| last shipment       = 
| release price       = 

| family              = OCTEON
| series              = CN3800
| locked              = 
| frequency           = 400 MHz
| bus type            = 
| bus speed           = 
| bus rate            = 
| bus links           = 
| clock multiplier    = 

| isa family          = MIPS
| isa                 = MIPS64
| microarch           = cnMIPS
| platform            = 
| chipset             = 
| core name           = cnMIPS
| core family         = 
| core model          = 
| core stepping       = 
| process             = 130 nm
| transistors         = 
| technology          = CMOS
| die area            = <!-- XX mm² -->
| die width           = 
| die length          = 
| word size           = 64 bit
| core count          = 12
| thread count        = 12
| max cpus            = 1
| max memory          = 16 GiB
| max memory addr     = 

| electrical          = 
| power               = 
| v core              = 
| v core tolerance    = 
| v io                = 
| v io tolerance      = 
| v io 2              = 
| v io 3              = 
| sdp                 = 
| tdp                 = 
| tdp typical         = 
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = 
| temp max            = 
| tjunc min           = <!-- .. °C -->
| tjunc max           = 
| tcase min           = 
| tcase max           = 
| tstorage min        = 
| tstorage max        = 
| tambient min        = 
| tambient max        = 

|package module 1={{packages/cavium/fcbga-1521}}
}}
The '''CN3850-400 NSP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

== Cache ==
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
{{cache size
|l1 cache=480 KiB
|l1i cache=384 KiB
|l1i break=12x32 KiB
|l1i desc=64-way set associative
|l1d cache=96 KiB
|l1d break=12x8 KiB
|l1d desc=64-way set associative
|l1d policy=Write-through
|l2 cache=1 MiB
|l2 break=1x1 MiB
|l2 desc=8-way set associative
}}

== Memory controller ==
{{memory controller
|type=DDR2-800
|ecc=Yes
|max mem=16 GiB
|controllers=1
|channels=1
|width=128 bit
|max bandwidth=11.92 GiB/s
|bandwidth schan=11.92 GiB/s
}}

== Expansions ==
{{expansions
|pcix width=64 bit
|pcix clock=133.33 MHz
|pcix rate=1,017.25 MiB/s
|pcix extra=host or slave
|uart=yes
|uart ports=2
|gp io=Yes
}}

== Networking ==
{{network
|mii opts=Yes
|rgmii=yes
|rgmii ports=8
|spi opts=Yes
|spi42=Yes
|spi42 ports=2
}}

== Hardware Accelerators ==
{{accelerators
|encryption=Yes
|encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
|regex=Yes
|regex feature=16 Engines
|compression=Yes
|decompression=Yes
|tcp=Yes
|qos=Yes
}}

== Block diagram ==
[[File:octeon cn38xx block diagram.png|750px]]

== Datasheet ==
* [[:File:octeon cn38xx and cn36xx product brief.pdf|OCTEON CN38XX/CN36XX 4 to 16-Core Product Brief]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN3850-400 NSP - Cavium#package +
base frequency	400 MHz (0.4 GHz, 400,000 kHz) +
core count	12 +
core name	cnMIPS +
designer	Cavium +
family	OCTEON +
first announced	September 13, 2004 +
first launched	June 1, 2005 +
full page name	cavium/octeon/cn3850-400bg1521-nsp +
has ecc memory support	true +
has hardware accelerators for cryptography	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for regular expression	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	480 KiB (491,520 B, 0.469 MiB) +
l1d$ description	64-way set associative +
l1d$ size	96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description	64-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	8-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	June 1, 2005 +
main image	+
manufacturer	TSMC +
market segment	Networking +
max cpu count	1 +
max memory	16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN3850-400 NSP +
name	Cavium CN3850-400 NSP +
package	FCBGA-1521 +
part number	CN3850-400BG1521-NSP +
process	130 nm (0.13 μm, 1.3e-4 mm) +
series	CN3800 +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	12 +
word size	64 bit (8 octets, 16 nibbles) +