Editing arm holdings/microarchitectures/cortex-a53

{{armh title|Cortex-A53|arch}}
{{microarchitecture
|atype=CPU
|name=Cortex-A53
|designer=ARM Holdings
|manufacturer=TSMC
|manufacturer 2=Samsung
|manufacturer 3=GlobalFoundries
|manufacturer 4=SMIC
|introduction=October 30, 2012
|process=28 nm
|process 2=20 nm
|process 3=16 nm
|process 4=14 nm
|process 5=10 nm
|cores=1
|cores 2=2
|cores 3=3
|cores 4=4
|type=In-order
|oooe=No
|speculative=Yes
|renaming=No
|stages=8
|decode=2-way
|isa=ARMv8
|feature=Hardware virtualization
|extension=FPU
|extension 2=NEON
|extension 3=TrustZone
|l1i=8-64 KiB
|l1i per=core
|l1i desc=2-way set associative
|l1d=8-64 KiB
|l1d per=core
|l1d desc=4-way set associative
|l2=128 KiB - 2 MiB
|l2 per=cluster
|l2 desc=16-way set associative
|predecessor=Cortex-A7
|predecessor link=arm_holdings/microarchitectures/cortex-a7
|successor=Cortex-A55
|successor link=arm_holdings/microarchitectures/cortex-a55
|pipeline=Yes
|issues=2

|cache=Yes
|core names=<!-- Yes if specify -->
|succession=Yes
}}
'''Cortex-A53''' (formerly '''Apollo''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A7|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}} or {{armh|Cortex-A72|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance.

Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.

== Process Technology ==
{{empty section}}

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable || Arch-Target
|-
| [[GCC]] || <code>-march=armv8-a</code> || <code>-mtune=cortex-a53</code> || <code>-mcpu=cortex-a53</code>
|-
| [[LLVM]] || <code>-march=armv8-a</code> || <code>-mtune=cortex-a53</code> || <code>-mcpu=cortex-a53</code>
|}

Note that for big.LITTLE system it's possible specify more specific performance tunes:

* <code>-mtune=cortex-a57.cortex-a53</code>
* <code>-mtune=cortex-a72.cortex-a53</code>
* <code>-mtune=cortex-a73.cortex-a53</code>

== Architecture ==
{{empty section}}

== Die ==
{{empty section}}

== All Cortex-A53 Chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="25">List of all Cortex-A53 Chips</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th></tr>
{{comp table header 1|cols=Launched, Designer, Family, Process, Core, C, T, L2$, L3$, Frequency, Max Mem, Designer, Name, Frequency}}
{{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]]
 |?full page name
 |?model number
 |?first launched
 |?designer
 |?microprocessor family
 |?process
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?max memory#GiB
 |?integrated gpu designer
 |?integrated gpu
 |?integrated gpu base frequency
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=15
 |mainlabel=-
 |limit=100
 |valuesep=,
}}
{{comp table count|ask=[[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]]}}
</table>
{{comp table end}}
codename	Cortex-A53 +
core count	1 +, 2 +, 3 + and 4 +
designer	ARM Holdings +
first launched	October 30, 2012 +
full page name	arm holdings/microarchitectures/cortex-a53 +
instance of	microarchitecture +
instruction set architecture	ARMv8 +
manufacturer	TSMC +, Samsung + and GlobalFoundries +
microarchitecture type	CPU +
name	Cortex-A53 +
pipeline stages	8 +
process	40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) +