Editing arm/armv1

{{arm title|ARMv1}}
'''ARMv1''' is the first [[ARM]] instruction set version. Introduced with the {{armh|ARM1}} on April 26 1985, the ARMv1 defines a {{arch|32}} ISA along with {{arm|26-bit|26-bit addressing space}}. The ARMv1 was only implemented by the {{armh|ARM1}} and was replaced soon after by the {{armh|ARM2}}. Only a few hundred of those chips were ever fabricated.

== Overview ==
The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a [[program counter]] which is 26 bits in size allowing for an address space of up to 64 MiB of data.

== Registers ==
There are 16 [[general purpose registers|general purpose]] 32-bit registers. With the exception of {{arm|R15|register 15}}, all registers are orthogonal with no specific designated purpose.

== Instruction Listing ==
The ARMv1 is broken down into 8 classes of instruction:

* [[#movement_instructions|Movement Instructions]]
* [[#load_instructions|Load Instructions]]
* [[#store_instructions|Store Instructions]]
* [[#arithmetic_instructions|Arithmetic Instructions]]
* [[#logical_instructions|Logical Instructions]]
* [[#comparison_instructions|Comparison Instructions]]
* [[#branch_instructions|Branch Instructions]]
* [[#miscellaneous_instructions|Miscellaneous Instructions]]

{{isa
| title    = ARMv1 ISA
| Syntax
| Description
| Action
| cols = 5
| listing  =

{{inst|cols=5|section=<span id="movement_instructions">'''Movement Instructions'''</span>}}
{{inst|mn=MOV |col 1=MOV<cond>{S} Rd, #imm            |col 2=Move value immed     |col 3 = Rd = immed}}
{{inst|mn=MOV |col 1=MOV<cond>{S} Rd, Rm, {, <shift>} |col 2=Move value           |col 3 = Rd = {shifted Rm} }}
{{inst|mn=MVN |col 1=MVN<cond>{S} Rd, #imm            |col 2=Move NOT value immed |col 3 = Rd = {{l|not|immed}}}}
{{inst|mn=MVN |col 1=MVN<cond>{S} Rd, Rm, {, <shift>} |col 2=Move NOT value       |col 3 = Rd = {{l|not|{shifted Rm} }}}}

{{inst|cols=5|section=<span id="load_instructions">'''Load Instructions'''</span>}}
{{inst|mn=LDM  |col 1=LDM<cond><type> Rn{!}, <reglist>{^} |col 2= Load multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Rd = [addr]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;update address based on {type} }}
{{inst|mn=LDR  |col 1=LDR<cond>{B} Rd, [Rn {, #imm}]{!}   |col 2=Load register immed |col 3 = Rd = [Rn + imm]<br>If !: Rn = Rn + imm}}
{{inst|mn=LDR  |col 1=LDR<cond>{B} Rd,  [Rn, Rm {, <shift>}]{!}  |col 2=Load register     |col 3 = Rd = [Rn + {shifted Rm}]<br>If !: Rn = Rn + {shifted Rm}]}}
{{inst|mn=LDR  |col 1=LDR<cond>{B}{T} Rd,  [Rn], #imm  |col 2=Load register, post index     |col 3 = Rd = [Rn]<br>Rn = Rn + imm}}
{{inst|mn=LDR  |col 1=LDR<cond>{B}{T} Rd,  [Rn], Rm {, <shift>}  |col 2=Load register, post index     |col 3 = Rd = [Rn]<br>Rn = Rn + {shifted Rm} }}

{{inst|cols=5|section=<span id="store_instructions">'''Store Instructions'''</span>}}
{{inst|mn=STM  |col 1=STM<cond><type> Rn{!}, <reglist>{^} |col 2= Store multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[addr] = Rd<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;update address based on {type} }}
{{inst|mn=STR  |col 1=STR<cond>{B} Rd, [Rn {, #imm}]{!}   |col 2=Store register immed |col 3 = [Rn + imm] = Rd<br>If !: Rn = Rn + imm}}
{{inst|mn=STR  |col 1=STR<cond>{B} Rd,  [Rn, Rm {, <shift>}]{!}  |col 2=Store register     |col 3 = [Rn + {shifted Rm}] = Rd<br>If !: Rn = Rn + {shifted Rm}]}}
{{inst|mn=STR  |col 1=STR<cond>{B}{T} Rd,  [Rn], #imm  |col 2=Store register, post index     |col 3 = [Rn] = Rd<br>Rn = Rn + imm}}
{{inst|mn=STR  |col 1=STR<cond>{B}{T} Rd,  [Rn], Rm {, <shift>}  |col 2=Store register, post index     |col 3 = [Rn] = Rd<br>Rn = Rn + {shifted Rm} }}

{{inst|cols=5|section=<span id="arithmetic_instructions">'''Arithmetic Instructions'''</span>}}
{{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, #imm           |col 2=Add and carry immed               |col 3 =Rd = Rn + imm + C}}
{{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Add and carry                     |col 3 =Rd = Rn + {shifted Rm} + C}}
{{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, #imm             |col 2=Add immed                         |col 3 =Rd = Rn + imm}}
{{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Add                               |col 3 =Rd = Rn + {shifted Rm} }}
{{inst|mn=RSB |col 1=RSB<cond>S Rd, Rn, #imm             |col 2=Reverse subtract immed            |col 3 =Rd = imm - Rn}}
{{inst|mn=RSB |col 1=RSB<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Reverse subtract                  |col 3 =Rd = {shifted Rm} - Rn }}
{{inst|mn=RSC |col 1=RSB<cond>S Rd, Rn, #imm             |col 2=Reverse subtract with carry immed |col 3 =Rd = imm - Rn - {{l|not|C}}}}
{{inst|mn=RSC |col 1=RSB<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Reverse subtract with carry       |col 3 =Rd = {shifted Rm} - Rn - {{l|not|C}}}}
{{inst|mn=SBC |col 1=SBC<cond>{S} Rd, Rn, #imm           |col 2=Subtract with carry immed         |col 3 =Rd = Rn - imm - {{l|not|C}}}}
{{inst|mn=SBC |col 1=SBC<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Subtract with carry               |col 3 =Rd = Rn - {shifted Rm} - {{l|not|C}}}}
{{inst|mn=SUB |col 1=SUB<cond>{S} Rd, Rn, #imm           |col 2=Subtract immed                    |col 3 =Rd = Rn - imm}}
{{inst|mn=SUB |col 1=SUB<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Subtract                          |col 3 =Rd = Rn - {shifted Rm} }}

{{inst|cols=5|section=<span id="logical_instructions">'''Logical Instructions'''</span>}}
{{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, #imm          |col 2=AND immed          |col 3 =Rd = {{l|land2|Rn|imm}}}}
{{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=AND                |col 3 =Rd = {{l|land2|Rn|{shifted Rm} }}}}
{{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, #imm          |col 2=Bit clear immed    |col 3 =Rd = {{l|land2|Rn|{{l|not|imm}}}}}}
{{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Bit clear          |col 3 =Rd = {{l|land2|Rn|{{l|not|Rm}}}}}}
{{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, #imm          |col 2=Exclusive OR immed |col 3 =Rd = {{l|xor|Rn|imm}}}}
{{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Exclusive OR       |col 3 =Rd = {{l|xor|Rn|{shifted Rm} }}}}
{{inst|mn=ORR |col 1=ORR<cond>{S} Rd, Rn, #imm          |col 2=Logical OR immed   |col 3 =Rd = {{l|lor2|Rn|imm}}}}
{{inst|mn=ORR |col 1=ORR<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Logical OR         |col 3 =Rd = {{l|lor2|Rn|{shifted Rm} }}}}

{{inst|cols=5|section=<span id="comparison_instructions">'''Comparison Instructions'''</span>}}
{{inst|mn=CMN   |col 1=CMN<cond> Rn, #imm          |col 2=Compare negative immed |col 3 =CPSR flags set on (Rn + imm)}}
{{inst|mn=CMN   |col 1=CMN<cond> Rn, Rm{, <shift>} |col 2=Compare negative       |col 3 =CPSR flags set on (Rn + {shifted Rm})}}
{{inst|mn=CMP   |col 1=CMP<cond> Rn, #imm          |col 2=Compare immed          |col 3 =CPSR flags set on (Rn - imm)}}
{{inst|mn=CMP   |col 1=CMP<cond> Rn, Rm{, <shift>} |col 2=Compare                |col 3 =CPSR flags set on (Rn - {shifted Rm})}}
{{inst|mn=TEQ   |col 1=TEQ<cond> Rn, #imm          |col 2=Test equality immed    |col 3 =CPSR flags set on ({{l|xor|Rn|imm}})}}
{{inst|mn=TEQ   |col 1=TEQ<cond> Rn, Rm{, <shift>} |col 2=Test equality          |col 3 =CPSR flags set on ({{l|xor|Rn|{shifted Rm} }})}}
{{inst|mn=TST   |col 1=TST<cond> Rn, #imm          |col 2=Test bits immed        |col 3 =CPSR flags set on ({{l|land2|Rn|imm}})}}
{{inst|mn=TST   |col 1=TST<cond> Rn, Rm{, <shift>} |col 2=Test bits              |col 3 =CPSR flags set on ({{l|land2|Rn|{shifted Rm} }})}}

{{inst|cols=5|section=<span id="branch_instructions">'''Branch Instructions'''</span>}}
{{inst|mn=B  |col 1=B<cond> imm  |col 2=Branch relative |col 3 =PC = PC + address}}
{{inst|mn=BL |col 1=BL<cond> imm |col 2=Branch and link relative |col 3 =LR = RET<br>PC = PC + address}}

{{inst|cols=5|section=<span id="miscellaneous_instructions">'''Miscellaneous Instructions'''</span>}}
{{inst|mn=SWI |col 1=SWI<cond> imm |col 2=Software interrupt |col 3 =LR = RET<br>Execute SWI vector in supervisor mode}}
}}