Editing cavium/octeon plus/cn5860-1000bg1521-exp

{{cavium title|CN5860-1000 EXP}}
{{mpu
| name                = Cavium CN5860-1000 EXP
| no image            = 
| image               = octeon plus chip.png
| image size          = 
| caption             = 
| designer            = Cavium
| manufacturer        = TSMC
| model number        = CN5860-1000 EXP
| part number         = CN5860-1000BG1521-EXP
| part number 1       = 
| part number 2       = 
| part number 3       = 
| market              = Network
| first announced     = October 9, 2006
| first launched      = February, 2007
| last order          = 
| last shipment       = 
| release price       = 

| family              = OCTEON Plus
| series              = CN58xx
| locked              = 
| frequency           = 1,000 MHz
| bus type            = 
| bus speed           = 
| bus rate            = 
| bus links           = 
| clock multiplier    = 

| isa family          = MIPS
| isa                 = MIPS64
| microarch           = cnMIPS
| platform            = 
| chipset             = 
| core name           = 
| core family         = 
| core model          = 
| core stepping       = 
| process             = 90 nm
| transistors         = 
| technology          = CMOS
| die area            = <!-- XX mm² -->
| die width           = 
| die length          = 
| word size           = 64 bit
| core count          = 16
| thread count        = 16
| max cpus            = 1
| max memory          = 
| max memory addr     = 


| power               = 40 W
| v core              = 
| v core tolerance    = 
| v io                = 
| v io tolerance      = 
| v io 2              = 
| v io 3              = 
| sdp                 = 
| tdp                 = 
| tdp typical         = 
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = 
| temp max            = 
| tjunc min           = 
| tjunc max           = 
| tcase min           = 
| tcase max           = 
| tstorage min        = 
| tstorage max        = 
| tambient min        = 
| tambient max        = 

|package module 1={{packages/cavium/fcbga-1521}}
}}
'''CN5860-1000 EXP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] network microprocessor designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as [[RegEx]], compression/decompression, and TCP acceleration.


== Cache ==
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
{{cache size
|l1 cache=768 KiB
|l1i cache=512 KiB
|l1i break=16x32 KiB
|l1i desc=64-way set associative
|l1d cache=256 KiB
|l1d break=16x16 KiB
|l1d desc=64-way set associative
|l2 cache=2 MiB
|l2 break=1x2 MiB
|l2 desc=8-way set associative
}}

== Memory controller ==
{{memory controller
|type=DDR2-800
|ecc=Yes
|max mem=
|controllers=1
|channels=1
|width=128 bit
|max bandwidth=11.92 GiB/s
|bandwidth schan=11.92 GiB/s
}}

== Expansions ==
{{expansions
|pcix width=64 bit
|pcix clock=133.33 MHz
|pcix rate=1,017.25 MiB/s
|pcix extra=host or slave
|uart=yes
|uart ports=2
|gp io=Yes
}}

== Networking ==
{{network
|mii opts=Yes
|rgmii=yes
|rgmii ports=8
|spi opts=Yes
|spi42=Yes
|spi42 ports=2
}}

== Hardware Accelerators ==
{{accelerators
|regex=Yes
|regex feature=32 Engines
|compression=Yes
|decompression=Yes
|tcp=Yes
|qos=Yes
}}

== Block diagram ==
[[File:octeon plus cn58xx.png|750px]]

== Datasheet ==
* [[:File:octeon plus cn58xx (rev 1.4).pdf|OCTEON CN58XX Processors Product Brief]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN5860-1000 EXP - Cavium#package +
base frequency	1,000 MHz (1 GHz, 1,000,000 kHz) +
core count	16 +
designer	Cavium +
family	OCTEON Plus +
first announced	October 9, 2006 +
first launched	February 2007 +
full page name	cavium/octeon plus/cn5860-1000bg1521-exp +
has ecc memory support	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for regular expression	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	64-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	64-way set associative +
l1i$ size	512 KiB (524,288 B, 0.5 MiB) +
l2$ description	8-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	February 2007 +
main image	+
manufacturer	TSMC +
market segment	Network +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN5860-1000 EXP +
name	Cavium CN5860-1000 EXP +
package	FCBGA-1521 +
part number	CN5860-1000BG1521-EXP +
power dissipation	40 W (40,000 mW, 0.0536 hp, 0.04 kW) +
process	90 nm (0.09 μm, 9.0e-5 mm) +
series	CN58xx +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	16 +
word size	64 bit (8 octets, 16 nibbles) +