Editing ambric/am2000/am2035

{{ambric title|Am2035}}
{{mpu
| name                = Am2035
| no image            = Yes
| image               = 
| image size          = 
| caption             = 
| designer            = Ambric
| manufacturer        = 
| model number        = Am2035
| part number         = Am2035
| market              = Embedded
| first announced     = October 10, 2006
| first launched      = January 2007
| last order          = 2012
| last shipment       = 2012

| family              = Am2000
| series              = Gen 1
| locked              = No
| frequency           = 333 MHz
| bus type            = 
| bus speed           = 100 MHz
| bus rate            = 
| clock multiplier    = 3.3

| microarch           = Ambric 
| platform            = 
| chipset             = 
| core name           = 
| core family         = 
| core model          = 
| core stepping       = 
| process             = 130 nm
| transistors         = 
| technology          = CMOS
| die size            = 
| word size           = 32 bit
| core count          = 280
| thread count        = 
| max cpus            = 
| max memory          = 4 GiB

| electrical          = 
| power               = 
| v core              = 
| v core tolerance    = 
| sdp                 = 
| tdp                 = 
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = 
| temp max            = 
| tjunc min           = 
| tjunc max           = 
| tcase min           = 
| tcase max           = 
| tstorage min        = 
| tstorage max        = 

| packaging           = 
| package 0           = 
| package 0 type      = 
| package 0 pins      = 
| package 0 pitch     = 
| package 0 width     = 
| package 0 length    = 
| package 0 height    = 
| socket 0            = 
| socket 0 type       = 
}}
'''Am2035''' was an [[MPPA]] introduced in late 2006 by [[Ambric]]. This model was made of {{ambric|am2000#Architecture|35 Brics}} arranged as a grid, making up a total of 280 {{arch|32}} [[RICS]]-like cores operating asynchronously at 1-333 MHz.

== Architecture ==
{{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}}
The Am2035 is made of 35 homogeneous 'Brics' laid out in a grid to form 280 cores and 280 RAM units.

General layout:
* 35x Brics
** 2x Computer Unit (CU)
*** 2x SRD {{arch|32}} CPU
*** 2x RD {{arch|32}} CPU
** 2x [[RAM]] Unit (RU)
*** 4x 2 KB [[SRAM]] bank

== Cache ==
The Am2035 contains 35 Brics, each with its own [[RAM]] Unit (RU) of 13 kB of SRAM for a total of 455 kB of SRAM.

== Memory controller ==
{{integrated memory controller
| type               = DDR2-400
| controllers        = 2
| channels           = 1
| ecc support        = 
| max bandwidth      = 
| bandwidth schan    = 
| bandwidth dchan    = 
| max memory         = 4 GiB
}}

== Expansions ==
* [[has feature::PCIe]]
* [[has feature::JTAG]]
* [[has feature::GPIO]] @ 100 MHz
* [[has feature::serial flash]]
base frequency	333 MHz (0.333 GHz, 333,000 kHz) +
bus speed	100 MHz (0.1 GHz, 100,000 kHz) +
clock multiplier	3.3 +
core count	280 +
designer	Ambric +
family	Am2000 +
first announced	October 10, 2006 +
first launched	January 2007 +
full page name	ambric/am2000/am2035 +
has feature	PCIe +, JTAG +, GPIO + and serial flash +
has locked clock multiplier	false +
instance of	microprocessor +
last order	2012 +
last shipment	2012 +
ldate	January 2007 +
market segment	Embedded +
max memory	4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
microarchitecture	Ambric +
model number	Am2035 +
name	Am2035 +
part number	Am2035 +
process	130 nm (0.13 μm, 1.3e-4 mm) +
series	Gen 1 +
technology	CMOS +
word size	32 bit (4 octets, 8 nibbles) +