Editing dec/microarchitectures/alpha 21164

{{dec title|Alpha 21164|arch}}
{{microarchitecture
|atype=CPU
|name=Alpha 21164
|designer=DEC
|manufacturer=DEC
|introduction=January, 1995
|process=0.5 µm
|cores=1
|type=Superscalar
|oooe=No
|speculative=Yes
|renaming=No
|stages min=7
|stages max=9
|decode=4-way
|isa=Alpha
|l1i=8 KiB
|l1i per=core
|l1i desc=direct-mapped
|l1d=8 KiB
|l1d per=core
|l1d desc=direct-mapped
|l2=96 KiB
|l2 per=core
|l2 desc=3-way set associative
|l3=1-64 MiB
|l3 per=motherboard
|l3 desc=direct-mapped
|predecessor=Alpha 21064
|predecessor link=dec/microarchitectures/alpha_21064
|successor=Alpha 21264
|successor link=compaq/microarchitectures/alpha_21264
}}
'''Alpha 21164''' was an [[Alpha]] microarchitecture designed by [[DEC]] and introduced in 1995 as a successor to the {{\\|Alpha 21064}} architecture.
codename	Alpha 21164 +
core count	1 +
designer	DEC +
first launched	January 1995 +
full page name	dec/microarchitectures/alpha 21164 +
instance of	microarchitecture +
instruction set architecture	Alpha +
manufacturer	DEC + and Samsung +
microarchitecture type	CPU +
name	Alpha 21164 +
pipeline stages (max)	12 +
pipeline stages (min)	7 +
process	500 nm (0.5 μm, 5.0e-4 mm) +