Editing arm holdings/microarchitectures/cortex-a55

{{armh title|Cortex-A55|arch}}
{{microarchitecture
|atype=CPU
|name=Cortex-A55
|designer=ARM Holdings
|manufacturer=TSMC
|manufacturer 2=Samsung
|manufacturer 3=GlobalFoundries
|manufacturer 4=SMIC
|introduction=May 29, 2017
|process=20 nm
|process 2=16 nm
|process 3=14 nm
|process 4=10 nm
|process 5=
|cores=1
|cores 2=2
|cores 3=3
|cores 4=4
|type=In-order
|oooe=No
|speculative=No
|renaming=No
|stages=8
|decode=2-way
|isa=ARMv8
|feature=Hardware virtualization
|extension=FPU
|extension 2=NEON
|extension 3=TrustZone
|l1i=8-64 KiB
|l1i per=core
|l1i desc=2-way set associative
|l1d=8-64 KiB
|l1d per=core
|l1d desc=4-way set associative
|l2=64-256 KiB
|l2 per=core
|l2 desc=
|l3=0-4 MiB
|l3 per=Cluster
|predecessor=Cortex-A7
|predecessor link=arm_holdings/microarchitectures/cortex-a7
|successor=Cortex-A55
|successor link=arm_holdings/microarchitectures/cortex-a55
}}
codename	Cortex-A55 +
core count	1 +, 2 +, 3 + and 4 +
designer	ARM Holdings +
first launched	May 29, 2017 +
full page name	arm holdings/microarchitectures/cortex-a55 +
instance of	microarchitecture +
instruction set architecture	ARMv8.2 +
manufacturer	TSMC +, Samsung +, GlobalFoundries + and SMIC +
microarchitecture type	CPU +
name	Cortex-A55 +
pipeline stages	8 +
process	16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +