Editing intel/xeon e5

{{intel title|Xeon E5}}
{{ic family
| extended family   = 
| title             = Intel Xeon E5
| image             = 
| caption           = 
| no image          = Yes
| developer         = Intel
| manufacturer      = Intel
| type              = Microprocessors
| first announced   = April 5, 2011
| first launched    = April 5, 2011
| production start  = 
| production end    = 
| arch              = Multi-socket server microprocessors
| isa               = x86-64
| microarch         = Westmere
| microarch 2       = Ivy Bridge
| microarch 3       = Haswell
| microarch 4       = Broadwell
| word              = 64 bit
| proc              = 32 nm
| proc 2            = 22 nm
| proc 3            = 14 nm
| proc 4            = 
| tech              = CMOS
| tech 2            = 
| clock min         = 1700 MHz
| clock max         = 3400 MHZ
| package           = FCLGA-2011-v3
| package 2         = 
| socket            = LGA-2011-v3
| socket 2          = 

| succession       = <!-- yes for succession info -->
| predecessor      = 
| predecessor link = 
| successor        = 
| successor link   = 
}}
'''Xeon E5''' is a family of mid-range enterprise-level [[x86]] microprocessors. These server processors offer high performance, multi-socket configuration support, and an extensive set of features. Various models are also used as high-end workstation microprocessors.

== Members ==
=== Westmere EP ===
{{see also|intel/microarchitectures/westmere|l1=Westmere µarch}}
{{empty section}}

=== Ivy Bridge EP (v2) ===
{{main|intel/microarchitectures/ivy bridge|l1=Ivy Bridge µarch}}
{{empty section}}

=== Haswell EP (v3) ===
{{main|intel/microarchitectures/haswell|l1=Haswell µarch}}
{{empty section}}

=== Broadwell EP (v4) ===
{{main|intel/microarchitectures/broadwell|l1=Broadwell µarch}}
Launched in mid-[[2016]] Xeon E5 V4 models are based on the {{intel|Broadwell|l=arch}} microarchitecture and are manufactured on [[Intel]]'s [[14 nm process]]. This series is composed of anywhere from [[4 cores|4]] up to [[22 cores]] configured in two rings with two bridges between them. Each ring passes data in opposite direction (i.e. one clockwise and the other counter-clockwise) in order to allow shortest path opportunities.

* All Broadwell EP models have {{intel|VT-x}}, {{intel|VT-d}}, {{intel|EPT}}, {{intel|EIST}}, {{intel|Flex Memory Access}}.
* All Broadwell EP models support {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|AVX2}}, {{x86|TXT}} and {{x86|TSX}}

==== Cache Coherency ====
{{main|intel/microarchitectures/broadwell#high_core_count|l1=Broadwell §  High Core Count}}
Broadwell EP has four snoop modes: Home Snoop (HS), Early Snoop (ES), Cluster-on-Die (COD) and Home Snoop with Directory and Opportunistic Snoop Broadcast (HS with DIR + OSB).

==== Die Stats ====
{| class="wikitable" style="text-align: center;"
|-
! colspan="3" style="background:#D6D6FF;" | Layout
|-
! Low Core Count (LCC) !! Medium Core Count (MCC) !! High Core Count (HCC)
|-
| Up to 10 Cores || 12-14 Cores || 16+ Cores
|-
| 246.24 mm² || 306.18 mm² || 456.12 mm²
|-
| ~3,200,000,000 Transistors || ~4,700,000,000 Transistors || ~7,200,000,000 Transistors
|-
|[[File:E5 v4 LCC.png|300px]] || [[File:E5 v4 MCC.png|300px]] || [[File:E5 v4 HCC.png|300px]]
|}


==== List of Models ====
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
                           or on the talk page of this article.
-->
<table class="wikitable sortable tc12 tc13 tc14 tc15" style="overflow-x: scroll; min-width: 1150px;">
<tr><th colspan="15" style="background:#D6D6FF;">Broadwell EP-based Xeon E5 Models</th></tr>
<tr><th colspan="15">Main processor</th></tr>
<tr><th>Model</th><th>Launched</th><th>Release Price</th><th>Sockets</th><th>Cores</th><th>Threads</th><th>L3$</th><th>Freq</th><th>Turbo</th><th>TDP</th><th>Max Mem</th><th>HT</th><th>vPro</th><th>TBT 2.0</th><th>TBMT 3.0</th></tr>
{{table sep|col=15|text=4S Environments}}
{{#ask: [[Category:microprocessor models by intel]][[microprocessor family::Xeon E5]][[microarchitecture::Broadwell]][[max cpu count::4]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?max cpu count
 |?core count
 |?thread count
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?max memory#TB
 |?has simultaneous multithreading
 |?has intel vpro technology
 |?has intel turbo boost technology 2_0
 |?has intel turbo boost max technology 3.0
 |format=template
 |template=proc table 3
 |userparam=16:13
 |mainlabel=-
}}
{{table sep|col=15|text=2S Environments}}
{{#ask: [[Category:microprocessor models by intel]][[microprocessor family::Xeon E5]][[microarchitecture::Broadwell]][[max cpu count::2]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?max cpu count
 |?core count
 |?thread count
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?max memory#TB
 |?has simultaneous multithreading
 |?has intel vpro technology
 |?has intel turbo boost technology 2_0
 |?has intel turbo boost max technology 3.0
 |format=template
 |template=proc table 3
 |userparam=16:13
 |mainlabel=-
}}
{{table sep|col=15|text=1S Environments}}
{{#ask: [[Category:microprocessor models by intel]][[microprocessor family::Xeon E5]][[microarchitecture::Broadwell]][[max cpu count::1]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?max cpu count
 |?core count
 |?thread count
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?max memory#TB
 |?has simultaneous multithreading
 |?has intel vpro technology
 |?has intel turbo boost technology 2_0
 |?has intel turbo boost max technology 3.0
 |format=template
 |template=proc table 3
 |userparam=16:13
 |mainlabel=-
}}
{{table count|col=15|ask=[[Category:microprocessor models by intel]][[microprocessor family::Xeon E5]][[microarchitecture::Broadwell]]}}
</table>

==== Documents ====
===== Datasheets =====
* [[:File:Intel Xeon Processor E5 v4 Product Family Datasheet, Volume One- Electrical.pdf|Intel Xeon Processor E5 v4 Product Family Datasheet, Volume One: Electrical Volume 1 of 2]]
* [[:File:Intel Xeon Processor E5 v4 Product Family Datasheet Volume 2- Registers.pdf|Intel Xeon Processor E5 v4 Product Family Datasheet Volume 2: Registers]]
* [[:File:Intel Xeon Processor E5 v4 Product Family Thermal Mechanical Specification and Design Guide.pdf|Intel Xeon Processor E5 v4 Product Family Thermal Mechanical Specification and Design Guide]]
===== Others =====
* [[:File:Intel Xeon Processor E5-2600 v4 Product Family Fact Sheet.pdf|Introducing the Intel Xeon Processor E5-2600 v4 Product Family]]
* [[:File:Intel Xeon Processor E5-2600 v4 Product Family Product Brief IoT.pdf|The Foundation for IoT Transformation; Intel Xeon Processor E5-2600 v4 Product Family IoT]]
* [[:File:Intel Xeon Processor E5-2600 v4 Product Family Product Brief.pdf|The Engine for Digital; Transformation in the Data Center; Intel Xeon Processor E5-2600 v4 Product Family]]
* [[:File:Intel Xeon Processor E5-4600 v4 Product Family Product Brief.pdf|Powerful, Dense 4-socket Servers for Next-Generation Data Center and Cloud Deployments]]

== See Also ==
* {{intel|Xeon}}
** {{intel|Xeon E7}}
** {{intel|Xeon E3}}
* {{amd|Opteron}}
designer	Intel +
first announced	April 5, 2011 +
first launched	April 5, 2011 +
full page name	intel/xeon e5 +
instance of	microprocessor family +
instruction set architecture	x86-64 +
main designer	Intel +
manufacturer	Intel +
microarchitecture	Westmere +, Ivy Bridge +, Haswell + and Broadwell +
name	Intel Xeon E5 +
package	FCLGA-2011-v3 +
process	32 nm (0.032 μm, 3.2e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
socket	LGA-2011-v3 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +