Editing cavium/octeon plus/cn5750-900bg1217-sp

{{cavium title|CN5750-900 SP}}
{{mpu
| name                = Cavium CN5750-900 SP
| no image            = 
| image               = Octeon CN57xx.svg
| image size          = 
| caption             = 
| designer            = Cavium
| manufacturer        = TSMC
| model number        = CN5750-900 SP
| part number         = CN5750-900BG1217-SP
| part number 1       = 
| part number 2       = 
| part number 3       = 
| market              = Storage
| first announced     = Jun 26, 2007
| first launched      = August, 2007
| last order          = 
| last shipment       = 
| release price       = 

| family              = OCTEON Plus
| series              = CN57xx
| locked              = 
| frequency           = 900 MHz
| bus type            = 
| bus speed           = 
| bus rate            = 
| bus links           = 
| clock multiplier    = 

| isa family          = MIPS
| isa                 = MIPS64
| microarch           = cnMIPS
| platform            = 
| chipset             = 
| core name           = 
| core family         = 
| core model          = 
| core stepping       = 
| process             = 90 nm
| transistors         = 
| technology          = CMOS
| die area            = <!-- XX mm² -->
| die width           = 
| die length          = 
| word size           = 64 bit
| core count          = 12
| thread count        = 12
| max cpus            = 1
| max memory          = 
| max memory addr     = 

| electrical          = 
| power               = 
| v core              = 
| v core tolerance    = 
| v io                = 
| v io tolerance      = 
| v io 2              = 
| v io 3              = 
| sdp                 = 
| tdp                 = 
| tdp typical         = 
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = 
| temp max            = 
| tjunc min           = 
| tjunc max           = 
| tcase min           = 
| tcase max           = 
| tstorage min        = 
| tstorage max        = 
| tambient min        = 
| tambient max        = 

| packaging           = Yes
| package 0           = FCBGA-1217
| package 0 type      = FCBGA
| package 0 pins      = 1217
| package 0 pitch     = 
| package 0 width     = 40 mm
| package 0 length    = 40 mm
| package 0 height    = 
| socket 0            = BGA-1217
| socket 0 type       = BGA
}}
'''CN5750-900 SP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration.

== Cache ==
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
{{cache size
|l1 cache=576 KiB
|l1i cache=384 KiB
|l1i break=12x32 KiB
|l1d cache=192 KiB
|l1d break=12x16 KiB
|l2 cache=2 MiB
|l2 break=1x2 MiB
}}

== Memory controller ==
{{memory controller
|type=DDR2-800
|ecc=Yes
|max mem=
|controllers=1
|channels=2
|width=64 bit
|max bandwidth=11.92 GiB/s
|bandwidth schan=5.96 GiB/s
|bandwidth dchan=11.92 GiB/s
}}

== Expansions ==
{{expansions
|pcie revision=1.0
|pcie lanes=8
|pcie config=x4
|pcie config 2=x8
|uart=yes
|gp io=Yes
}}

== Networking ==
Interface options:
* 8-lanes [[PCIe]] + 8-lanes PCIe
* 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
* 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
{{network
|mii opts=Yes
|sgmii=yes
|sgmii ports=4
|xaui=1
|xaui ports=1
}}

== Hardware Accelerators ==
{{accelerators
|compression=Yes
|decompression=Yes
|tcp=Yes
|qos=Yes
|raid=Yes
|raid5=Yes
|raid6=Yes
}}

== Block diagram ==
[[File:cn57xx block diagram.png|750px]]

== Datasheet ==
* [[:File:CN57XX PB Rev 1.2.pdf|OCTEON CN57XX Processors Product Brief]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN5750-900 SP - Cavium#package + and CN5750-900 SP - Cavium#io +
base frequency	900 MHz (0.9 GHz, 900,000 kHz) +
core count	12 +
designer	Cavium +
family	OCTEON Plus +
first announced	June 26, 2007 +
first launched	August 2007 +
full page name	cavium/octeon plus/cn5750-900bg1217-sp +
has ecc memory support	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
has hardware raid 5 support	true +
has hardware raid 6 support	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	576 KiB (589,824 B, 0.563 MiB) +
l1d$ size	192 KiB (196,608 B, 0.188 MiB) +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	August 2007 +
main image	+
manufacturer	TSMC +
market segment	Storage +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	2 +
max pcie lanes	8 +
microarchitecture	cnMIPS +
model number	CN5750-900 SP +
name	Cavium CN5750-900 SP +
package	FCBGA-1217 +
part number	CN5750-900BG1217-SP +
process	90 nm (0.09 μm, 9.0e-5 mm) +
series	CN57xx +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	12 +
word size	64 bit (8 octets, 16 nibbles) +