Editing cavium/octeon/cn3005-500bg350-cp

{{cavium title|CN3005-500 CP}}
{{mpu
| name                = Cavium CN3005-500 CP
| no image            = 
| image               = cn3005-15.png
| image size          = 
| caption             = 
| designer            = Cavium
| manufacturer        = TSMC
| model number        = CN3005
| part number         = CN3005-500BG350-CP
| part number 1       = 
| part number 2       = 
| part number 3       = 
| market              = Embedded
| first announced     = January 30, 2006 
| first launched      = May 1, 2006
| last order          = 
| last shipment       = 
| release price       = $39

| family              = OCTEON
| series              = CN3000
| locked              = 
| frequency           = 500 MHz
| bus type            = 
| bus speed           = 
| bus rate            = 
| bus links           = 
| clock multiplier    = 

| isa family          = MIPS
| isa                 = MIPS64
| microarch           = cnMIPS
| platform            = 
| chipset             = 
| core name           = cnMIPS
| core family         = 
| core model          = 
| core stepping       = 
| process             = 130 nm
| transistors         = 
| technology          = CMOS
| die area            = <!-- XX mm² -->
| die width           = 
| die length          = 
| word size           = 64 bit
| core count          = 1
| thread count        = 1
| max cpus            = 1
| max memory          = 2 GiB
| max memory addr     = 

| electrical          = Yes
| power               = 4 W
| v core              = 
| v core tolerance    = 
| v io                = 
| v io tolerance      = 
| v io 2              = 
| v io 3              = 
| sdp                 = 
| tdp                 = 
| tdp typical         = 
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = 
| temp max            = 
| tjunc min           = <!-- .. °C -->
| tjunc max           = 
| tcase min           = 
| tcase max           = 
| tstorage min        = 
| tstorage max        = 
| tambient min        = 
| tambient max        = 

| packaging           = Yes
| package 0           = BGA-350
| package 0 type      = BGA
| package 0 pins      = 350
| package 0 pitch     = 
| package 0 width     = 
| package 0 length    = 
| package 0 height    = 
| socket 0            = 
| socket 0 type       = 
}}
The '''CN3005-500 CP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory.

== Cache ==
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
{{cache size
|l1 cache=24 KiB
|l1i cache=16 KiB
|l1i break=1x16 KiB
|l1i desc=2-way set associative
|l1d cache=8 KiB
|l1d break=1x8 KiB
|l1d desc=64-way set associative
|l1d policy=Write-through
|l2 cache=64 KiB
|l2 break=1x64 KiB
|l2 desc=2-way set associative
}}

== Memory controller ==
{{memory controller
|type=DDR2-533
|ecc=Yes
|max mem=2 GiB
|controllers=1
|channels=1
|width=16 bit
|max bandwidth=1,017 MiB/s
|bandwidth schan=1,017 MiB/s
}}

== Expansions ==
{{expansions
|pci width=32 bit
|pci clock=66.66 MHz
|pci rate=254.31 MiB/s
|pci extra=host or slave
|usb revision=2.0
|usb ports=1
|usb rate=60 MB/s
|usb extra=host / PHY
|uart=yes
|uart ports=2
|gp io=Yes
}}

== Networking ==
{{network
|mii opts=Yes
|rgmii=yes
|rgmii ports=1
|gmii=yes
|gmii ports=1
|pcm=yes
}}

== Features ==
Hardware acceleration units:
* Hardware implementation for common security algorithms:
** DES, 3DES, AES (up to 256 bit), SHA1, SHA-2 up to SHA-512, RSA, DH
* QoS
* TCP Acceleration

== Block diagram ==
[[File:cn3005 block diagram.png|750px]]

== Datasheet ==
* [[:File:octeon cn30xx product brief.pdf|OCTEON CN30XX Processors Product Brief]]
base frequency	500 MHz (0.5 GHz, 500,000 kHz) +
core count	1 +
core name	cnMIPS +
designer	Cavium +
family	OCTEON +
first announced	January 30, 2006 +
first launched	May 1, 2006 +
full page name	cavium/octeon/cn3005-500bg350-cp +
has ecc memory support	false +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	24 KiB (24,576 B, 0.0234 MiB) +
l1d$ description	64-way set associative +
l1d$ size	8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description	2-way set associative +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
l2$ description	2-way set associative +
l2$ size	0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
ldate	May 1, 2006 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory	2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth	0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN3005-500 CP +
name	Cavium CN3005-500 CP +
part number	CN3005-500BG350-CP +
power dissipation	4 W (4,000 mW, 0.00536 hp, 0.004 kW) +
process	130 nm (0.13 μm, 1.3e-4 mm) +
series	CN3000 +
smp max ways	1 +
supported memory type	DDR2-533 +
technology	CMOS +
thread count	1 +
word size	64 bit (8 octets, 16 nibbles) +